Patents Examined by Larry T Mackall
  • Patent number: 11301170
    Abstract: A computer-implemented method, according to one embodiment, includes: receiving a sub-logical page read command for data stored in NVRAM at a first LBA, and creating a searchable entry which includes the first LBA. Data read from the NVRAM is also received, where the received data corresponds to a given LBA. In response to determining that the given LBA matches the first LBA of the searchable entry, a copy of the received data is stored in a buffer. Moreover, in response to determining that a received sub-logical page write command is for data stored in the NVRAM at the first LBA, the copy of the received data in the buffer is coalesced with data included in the sub-logical page write command to form a full-logical page write. Furthermore, instructions to perform the full-logical page write in the NVRAM are sent.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: April 12, 2022
    Assignee: International Business Machines Corporation
    Inventors: Kevin E. Sallese, Timothy Fisher, Andrew D. Walls
  • Patent number: 11301171
    Abstract: According to one embodiment, a memory system detects a first block in which an elapsed time from a time point at which the block has been filled with write data exceeds a first period. The memory system notifies a host of a list of identifiers capable of identifying valid data portions stored in the first block or a list of identifiers capable of identifying all data portions stored in the first block. When receiving, from the host, a first copy request specifying one or more valid data portions stored in the first block as copy target data and specifying the second block group as a copy destination block group, the memory system copies the one or more valid data portions specified as the copy target data from the first block to the second block group.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: April 12, 2022
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno
  • Patent number: 11301382
    Abstract: A system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is to perform operations including detecting a voltage of a power source for the memory device has dropped below a threshold voltage indicative of an imminent power loss and writing data to the memory device in response to the detecting. The operations further include measuring a characteristic of the data in response to detecting a power on of the memory device; determining an estimated amount of time for which the memory device was powered off based on results of the measuring; and in response to the estimated amount of time satisfying a first threshold criterion, updating a value for a temporal voltage shift of a block family of programmed data based on the estimated amount of time.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: April 12, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Michael Sheperek, Bruce A. Liikanen, Steven Michael Kientz
  • Patent number: 11281588
    Abstract: Techniques manage an input/output (I/O) operation. Such techniques involve estimating a first storage area in a storage device to be accessed by an upcoming random I/O operation, first data being stored in the estimated first storage area. Such techniques further involve, before the random I/O operation is executed, pre-fetching the first data from the first storage area into a cache associated with the storage device. Such techniques enable implementation of the cache pre-fetch for random I/O operations, thereby effectively improving the performance of data access.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: March 22, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Lifeng Yang, Ruiyong Jia, Xinlei Xu, Yousheng Liu, Jian Gao
  • Patent number: 11256428
    Abstract: Each drive in a cluster is organized into splits of a single size. The splits are used as protection group members for a selected RAID level. Individual clusters can be scaled up with a number of new drives that is less than the number of protection group members for the RAID level by redistributing some data/parity to splits of the new drives. Splits are selected for redistribution such that new protection groups are created. If the number of new drives is equal to or greater than the number of protection group members for the RAID level, then new clusters may be created using the new drives. Any remaining drives are used to scale-up individual clusters.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: February 22, 2022
    Assignee: Dell Products L.P.
    Inventors: Kuolin Hua, Kunxiu Gao, Evgeny Malkevich
  • Patent number: 11256614
    Abstract: Provided herein may be a memory controller and a method of operating the same. The memory controller for controlling a plurality of memory devices in which data is stored may include a host interface configured to receive a request and a logical address corresponding to the request from a host, a processor including multiple cores, each configured to receive the logical address from the host interface and generate mapping information indicating a mapping relationship between the logical address and a physical address and a bitmap storage configured to store a bitmap indicating which core of the multiple cores each of previously-received logical addresses is assigned, wherein the host interface assigns the logical address to one of the multiple cores based on the bitmap.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: February 22, 2022
    Assignee: SK hynix Inc.
    Inventors: Seung Ok Han, Seung Wan Jung
  • Patent number: 11237961
    Abstract: A storage device includes a semiconductor memory device and a controller. The semiconductor memory device includes a plurality of memory blocks. The controller controls an operation of the semiconductor memory device. The controller includes a device garbage collection controller configured to select a victim memory block among the plurality of memory blocks, generate victim LBA information including a logical block address of a valid page in the selected victim memory block, and transfer the victim LBA information to a host device.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: February 1, 2022
    Assignee: SK hynix Inc.
    Inventor: Eu Joon Byun
  • Patent number: 11237768
    Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a page buffer group configured to include a plurality of page buffers respectively coupled to a plurality of memory areas through a plurality of bit lines, a row decoder configured to select a memory area, on which an operation corresponding to a command is to be performed, from among the plurality of memory areas, based on a row address included in an address, a column decoder configured to transfer data to a page buffer of the plurality of page buffers according to a column address included in the address and an address controller configured to control the row decoder and the column decoder so that the data is stored in another memory area other than the selected memory area.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: February 1, 2022
    Assignee: SK hynix Inc.
    Inventor: Gi Pyo Um
  • Patent number: 11231854
    Abstract: Some embodiments relate to a method and a corresponding apparatus for estimating the wear of a non-volatile memory. Such a method may include determining a load profile with respect to a real access load occurring during a defined test period where the load profile indicates a respectively associated access load for accesses to a first NVM, and generating access data representing the determined load profile. The method further includes determining an estimated value for the wear of a particular second NVM in part on the basis of the access data.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: January 25, 2022
    Assignee: HYPERSTONE GMBH
    Inventors: Steffen Allert, Martin Roeder, Christoph Baumhof
  • Patent number: 11226901
    Abstract: A method for initializing functional blocks on an electronic chip includes writing a programmable broadcast address to one or more functional blocks in a broadcast group; setting the one or more functional blocks in the broadcast group to a broadcast enable mode; writing one or more transactions to the programmable broadcast address; and disabling the broadcast enable mode.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: January 18, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: John E. Tillema
  • Patent number: 11221964
    Abstract: The described technology is generally directed towards allocating adjacent file parts to different virtual cylinder groups mapped to storage devices in a storage array system. According to an embodiment, a system can comprise a processor and computer executable components that can comprise a file allocating component that can allocate a first part of a file to a first logical data block mapped to a first physical data block on a first storage device, and allocate a second part of the file to a second logical data block mapped to a second physical data block on a second storage device, the allocating being based on the second physical data block being on a different storage device than the first physical data block. The components can also comprise a storage device controller that can write the first and second parts of the file to the first and second physical data blocks.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: January 11, 2022
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventor: Ronald Steinke
  • Patent number: 11210219
    Abstract: Servicing I/O operations directed to a dataset that is synchronized across a plurality of storage systems, including: receiving, by a follower storage system, a request to modify the dataset; sending, from the follower storage system to a leader storage system, a logical description of the modification to the dataset; receiving, from the leader storage system, information describing the modification to the dataset; processing, by the follower storage system, the request to modify the dataset; receiving, from the leader storage system, an indication that the leader storage system has processed the request to modify the dataset; and acknowledging, by the follower storage system, completion of the request to modify the dataset.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: December 28, 2021
    Assignee: Pure Storage, Inc.
    Inventors: Deepak Chawla, David Grunwald, Steven Hodgson, Tabriz Holtz, Ronald Karr
  • Patent number: 11210178
    Abstract: Disclosed are systems and methods of synchronization between a source and a target. The synchronization relationship can be quickly and easily be created for disaster recovery, real-time backup and failover, thereby ensuring that data on the source is fully-protected at an off-site location or on another server or VM, for example, at another data center, a different building or elsewhere in the cloud. Common snapshots available on both the source and target can act as common recovery points. The common recovery points can be used to locate the most recent snapshot in common, between the source and target, to enable a delta sync of all subsequently written data at the source to the target after an offline event.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: December 28, 2021
    Assignee: BUURST, Inc.
    Inventors: Rick Gene Braddy, Benjamin Goodwyn
  • Patent number: 11204722
    Abstract: A content-aware storage system and method for use therewith are presented. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to receive an image; determine an amount of spare memory space; generate a lower-resolution version of the image, wherein a resolution level of the lower-resolution version of the image is based on the determined amount of spare memory space; and store the image and the lower-resolution version of the image in the memory. Other embodiments are provided.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: December 21, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Dinesh Kumar Agarwal, Amit Sharma
  • Patent number: 11204721
    Abstract: A memory sub-system configured to dynamically determine input/output sizes of write commands based on a media physical layout of a memory sub-system. The memory sub-system can identify, dynamically in response to write commands being selected for execution in media units of the memory sub-system, a portion of a media layout that maps from logical addresses identified by the write commands in the logical address space to physical addresses of memory units in the media units. Based on the media layout, an input/output size for a next write command is identified and transmitted to the host system in a response. The host system generates the next write command and configures the amount of data to be written through the next write command based on the input/output size identified in the response.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: December 21, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Sanjay Subbarao, Mark Ish
  • Patent number: 11194512
    Abstract: A data storage device may include: a nonvolatile memory device; and a controller configured to control a read operation of the nonvolatile memory device, wherein the controller includes: a memory configured to store workload pattern information; and a processor configured to check a workload pattern in a first period based on the workload pattern information, and decide on a read mode to be performed in a second period following the first period, according to the workload pattern of the first period.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: December 7, 2021
    Assignee: SK hynix Inc.
    Inventors: Min Gu Kang, Jin Soo Kim
  • Patent number: 11188240
    Abstract: Provided is an information processing system including plural information processing devices each of which is accessible using first authentication information that is given to each of users, that varies among the users, and that is common to the plural information processing devices, access to a specific service from an accessed information processing device among the plural information processing devices being permitted using second authentication information that is given for the specific service to each of the users and that varies among the users. The information processing system includes a display controller and a storage controller.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: November 30, 2021
    Assignee: FUJIFILM Business Innovation Corp.
    Inventor: Yosuke Shinnaka
  • Patent number: 11188263
    Abstract: The present disclosure relates to a method for data writing, a device and a storage medium, wherein the method includes acquiring a first data to be written and saving a plurality of sub-blocks of the first data in one or more designated aggregated queue of multiple aggregated queues according to an aggregation strategy; performing, in each designated aggregated queue, data interception on a plurality of sub-blocks in a current queue to obtain a second data to be written; and writing the second data in a storage device. The data distribution written in the storage device becomes more ideal by a multi-queue aggregation, and thus the method for data writing according to the embodiments of the present disclosure can reduce the time consumed in reading the storage device effectively.
    Type: Grant
    Filed: January 18, 2020
    Date of Patent: November 30, 2021
    Assignee: INNOGRIT TECHNOLOGIES CO., LTD.
    Inventors: Lei Li, Ying Chu, Qian Cheng, Qun Zhao
  • Patent number: 11182078
    Abstract: A data storage device and a method of operating the same are provided. The data storage device includes a first non-volatile memory device, a second non-volatile memory device, and a management module. The management module receives a multi-access command including first and second physical addresses which are different from each other from a host, generates and sends a first access command including the first physical address to the first non-volatile memory device, and generates and sends a second access command including the second physical address to the second non-volatile memory device. The data storage device performs the first and second access commands on the first and second physical addresses, respectively.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: November 23, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun Jin Yun, Sil Wan Chang
  • Patent number: 11169743
    Abstract: A just a bunch of flash solid-state drive cluster (JBOF) and a method for transmitting a data processing request include obtaining a data processing request sent by a storage controller, determining a type of the data processing request, and either forwarding the data processing request to the target solid state drive (SSD) when the type of the data processing request is a bypass type, or sending the data processing request to a computing unit in the JBOF and sending the data processing request processed by the computing unit to the target SSD when the type of the data processing request is a background computing type.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: November 9, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Xiaochu Li, Dahong Yan