Abstract: A controller controls an operation of a semiconductor memory device. The controller includes a request analyzer, a storage, and a garbage collection controller. The request analyzer generates invalid data information, based on an erase request received from a host. The storage stores a garbage collection reference table representing memory blocks excluded from selection as a victim block on which a garbage collection operation is to be performed, based on the invalid data information. The garbage collection controller controls the garbage collection operation on the semiconductor memory device, based on exclusion block information generated according to the garbage collection reference table.

Abstract: A backup data storage system includes non-volatile memory units, a disk interface coupled to at least some of the non-volatile memory units, a connection component that facilitates exchanging data with the backup data storage system, and a smart network interface controller, coupled to the disk interface and the connection component to provide tape emulation to a host coupled to the backup data storage system. The disk interface, the connection component, and the smart network interface controller may be coupled using a PCIe bus. Tape data written to the backup storage device may be stored on the non-volatile memory units. A processor coupled to the smart network interface controller and the disk interface may receive the data from the smart network interface controller and may provide the data to the disk interface to store the data on the non-volatile memory units. The connection component may be a FICON connection component.

Abstract: A USB-based cloud disk according to an embodiment is connected with a computer, and, when a write command on a sector is received from the computer, the USB-based cloud disk transmits data regarding the sector and a data path regarding the sector data to a remote repository.

Abstract: A storage device including a nonvolatile memory device is described. The storage device includes a controller that receives a write command and data from an external host device. The controller preferentially writes the data in an area based on a normal write policy when the data is associated with a normal write, and in an area based on a turbo write policy when the data is associated with a turbo write. The controller may also receive a read command, to read data from an area based on the read command, and output the data to the external host device. The controller may also move the data in response to move information of the read command when the read command is received together with move information.

Abstract: Disclosed is a storage device, which include a non-volatile memory device including a plurality of memory blocks, a buffer memory, and a storage controller that receives a first allocation request and first logical address information from a host, allocates logical addresses of the first logical address information to a first physical group of the plurality of memory blocks in response to the first allocation request, receives a first write request and first write data associated with the first logical address information, stores the first write data in the buffer memory, and writes the first write data stored in the buffer memory in memory blocks of the first physical group in response to the first write request. The first allocation request precedes the first write request.

Abstract: A method of data reduction in a block-based data storage system includes selecting a starting position in a block based on a deterministic function of block data content. Then for an unaligned block beginning at the selected starting position, a block digest (e.g., block hash) is generated and compared with stored block digests of stored data blocks. If there is a match, and the stored block matches the unaligned block, then a reference to the stored block is stored in place of the unaligned block, and otherwise the unaligned block and a corresponding digest are stored. The storing of references to already stored blocks, without the constraint of observing aligned-block boundaries, realizes increased savings of physical storage space.

Abstract: A block family associated with a memory device is initialized. An initial value of a power cycle count associated with the memory device is stored. Responsive to programming a block residing in the memory device, the block is associated with the block family. Responsive to determining that a current value of the power cycle count exceeds the initial value of the power cycle count, the block family is closed. Responsive to determining that a time period that has elapsed since initializing the block family exceeds a threshold period, the block family is closed.

Abstract: A memory system includes a nonvolatile memory having a plurality of nonvolatile memory chips incorporated therein, a control circuit that controls the nonvolatile memory, an MPU that controls the control circuit, and an interface circuit that communicates with a host, all of which are mounted on a board of the memory system, and the memory system further includes a bus switch that switches connection of a signal line between the control circuit and the nonvolatile memory chips.

Abstract: A data storage device that provides priority-based internal data movement includes a controller communicatively coupled to volatile memory and to non-volatile memory circuits, where the controller is configured to queue requests in a plurality of queues in the volatile memory, where each of the requests is associated with one of a plurality of internal data movement command types. The controller is also configured to select one of the plurality of queues based on a prioritization of the plurality of internal data movement command types. The controller is also configured to determine that the selected queue includes at least one request of the associated internal data movement command type. The controller is also configured to issue the at least one request from the selected queue to at least one of the non-volatile memory circuits.

Abstract: A controller of a memory sub-system can, responsive to providing a command completion signal to a host, mark a portion of a plurality of commands that are addressed to a same logical block of the memory devices, reorder the marked portion of the plurality of commands, wherein write commands from the marked portion of the plurality of commands are given priority over read commands from the marked portion of the plurality of commands, execute a newest write command from the marked portion of the plurality of commands prior to executing read commands, addressed to the same logical block, from the marked portion of the plurality of commands, and execute read commands from the marked portion of the plurality of commands in on an order in which the read commands were received and after the execution of the newest write command, wherein the read commands are executed responsive to an execution of the newest write command.

Abstract: The present technology relates to a memory device and a method of operating the same. The memory device includes a memory cell array including a plurality of memory cells, a data register connected to the memory cell array through a bit line and configured to store data sensed through the bit line, a cache register configured to cache the data stored in the data register, and a control logic configured to control a caching operation of receiving a cache read command from a memory controller and storing the data, which is stored in the data register, in the cache register, during a cache read period, in response to the cache read command, wherein the control logic controls the caching operation based on whether the cache read command is a first command received after receiving a normal read command from the memory controller.

Abstract: Powering random access memory (RAM) modules with non-volatile memory components may include providing, by a power supply, a first output voltage to one or more RAM modules, each RAM module of the one or more RAM modules comprising a volatile memory component and a non-volatile memory component; providing, by the power supply, a second output voltage to one or more system components distinct from the one or more RAM modules; detecting a power event; sending, by the power supply, in response to detecting the power event, a signal to the one or more RAM modules to initiate a save operation, wherein the save operation comprises storing, for each of the one or more RAM modules, data from the volatile memory component to the non-volatile memory component; and ceasing, by the power supply, the second output voltage while maintaining the first output voltage to facilitate the save operation.

Abstract: Techniques for issuing efficient writes to an erasure coded storage object in a distributed storage system via adaptive logging are provided. In one set of embodiments, a node of the system can receive a write request for updating one or more logical data blocks of the storage object and determine whether a size of the one or more logical data blocks meets or exceeds a threshold size. Upon determining that the size of the one or more logical data blocks meets or exceeds the threshold size, the node can allocate a segment in a capacity object of the storage object, write the one or more logical data blocks via a full stripe write to the segment, and write metadata for the one or more logical data blocks to a log record in a log of a metadata object of the storage object. The metadata written to the log record can include mappings between logical block addresses (LBAs) of the one or more logical data blocks and physical block addresses (PBAs) where the one or more logical data blocks reside in the segment.

Abstract: A system and method of securing a computer system by controlling write access to a storage medium by monitoring an application; detecting an attempt by the application to write data to said storage medium; interrogating a rules database in response to said detection; and permitting or denying write access to the storage medium by the application in dependence on said interrogation.

Abstract: According to one embodiment, a memory system includes a non-volatile memory including first and second block groups, and a controller that performs a first write operation for the first block group and the first or a second write operation for the second block group. A first or second number of bits is written into a memory cell in the first or the second write operation. The second number of bits is larger than the first number of bits. The controller allocates a block to a buffer as a write destination block in the first write operation based on a degree of wear-out of at least one block, and writes data from an external device into the buffer in the first write operation.

Abstract: In connection with a write operation, a memory controller transmits a first command sequence to a memory chip, thereby causing the memory chip to execute a first-stage program operation that includes a first operation and a first part of a second operation after the first operation, and a second command sequence to the memory chip after the first-stage program operation is executed, thereby causing the memory chip to execute a second-stage program operation that includes a second part of the second operation and no part of the first operation. During the first operation, a program voltage is applied a plurality of times while increasing the program voltage each of the times by a first step size. During the second operation, the program voltage is applied a plurality of times while increasing the program voltage each of the times by a second step size smaller than the first step size.

Abstract: Database objects are retrieved from a database and parsed into normalized cached data objects. The database objects are stored in the normalized cached data objects in a cache store, and tenant data requests are serviced from the normalized cached data objects. The normalized cached data objects include references to shared objects in a shared object pool that can be shared across different rows of the normalized cached data objects and across different tenant cache systems.

Abstract: A first storage node communicates with at least one second storage node. A physical disk included in the at least one second storage node is mapped as a virtual disk of the first storage node. The method may include: receiving a first write request, where the first write request carries first to-be-written data; striping the first to-be-written data to obtain striped data, and writing the striped data to a physical disk and/or the virtual disk of the first storage node; and recording a write location of the striped data. For example, the technical solution may be applied to a storage system that includes an NVMe SSD.

Abstract: An operation method of a storage device including first and second physical functions respectively corresponding to first and second hosts includes receiving performance information from each of the first and second hosts, setting a first weight value corresponding to the first physical function and a second weight value corresponding to the second physical function, based on the received performance information, selecting one of a first submission queue, a second submission queue, a third submission queue, and a fourth submission queue based on an aggregated value table, the first and second submission queues being managed by the first host and the third and fourth submission queues are managed by the second host, processing a command from the selected submission queue, and updating the aggregated value table based on a weight value corresponding to the processed command from among the first and second weights and input/output (I/O) information of the processed command.

Abstract: A host interface layer in a storage device is described. The host interface layer may include an arbitrator to select a first submission queue (SQ) from a set including at least the first SQ and a second SQ. The first SQ may be associated with a first Quality of Service (QoS) level, and the second SQ may be associated with a second QoS level. A command fetcher may retrieve an input/output (I/O) request from the first SQ. A command parser may place the I/O request in a first command queue from a set including at least the first command queue and a second command queue. The arbitrator may be configured to select the first SQ based at least in part on a first weight associated with the first SQ and a second weight associated with the second SQ.