Abstract: Methods, systems, and devices for life expectancy monitoring for memory devices are described. Some memory devices may degrade over time, and this degradation may include or refer to a reduction of an ability of the memory device to reliably store, read, process, or communicate information, among other degradation. In accordance with examples as disclosed herein, a system may include components configured for monitoring health or life expectancy of the memory device, such as components that perform comparisons between signals or other operating characteristics resulting from operating at the memory device and one or more threshold values that may be indicative of a life expectancy of the memory device. In various examples, a memory device may perform a subsequent operation based on such a comparison, or may provide an indication of a life expectancy to a host device based on one or more comparisons or determinations about health or life expectancy.

Abstract: During conversion and transfer of data from a physical machine to a virtual hard disk, a transmuter generates a catalog of contents of the physical machine. Catalog entries are compared to a set of alterations templates which alter matching data. The altered data is then stored in the virtual hard disk. Alterations templates may include filters that exclude unwanted or duplicated catalog entries, mapping filters that transfer source catalog entries to target locations on the virtual hard disk, and add-on filters that add additional data or location references to catalog entries. The disclosed process allows modifications to be made in a systematic way during data transfer.

Abstract: Memory regions may be protected based on occurrence of an event in a computing device. Subsystems of the computing device may store information in a memory controller identifying memory regions to be erased upon occurrence of an event, such as a system or subsystem crash. The memory controller may control erasing the memory regions in response to an indication associated with the event. A memory dump may be performed after the memory regions have been erased.

Abstract: A graph can be generated based on an access pattern associated with blocks of a memory device that have been accessed by a host system, wherein the graph comprises nodes representing at least a subset of the blocks that have been accessed by the host system and edges that are based on the access pattern, wherein each edge is associated with a respective probability value between a respective pair of nodes. A number of edges having respective probability values that satisfy a probability value threshold criterion can be determined. It can be determined whether the number of edges satisfies a decayed edge value condition. In response to determining that the number of edges does not satisfy the decayed edge value condition, the graph can be removed.

Abstract: A method includes: receiving, by a storage device from a core in a host, a request to provide exclusive resource to a command of a predefined submission queue of a non-volatile memory (NVM) set in the storage device, wherein the request pertains to operating the NVM set in a deterministic state; generating a virtual NVM set identifier for a virtual NVM set based on a predefined mapping of the predefined submission queue and the NVM set; determining a storage controller associated with the NVM set based on a predefined mapping of the predefined submission queue, the NVM set, and the virtual NVM set identifier; enabling at least one core to operate in a Predictable Latency Mode; and operating the storage controller and the NVM set in the deterministic state by allocating predetermined resources to execute the command and return data with a predictable latency.

Abstract: According to various aspects of the present disclosure, methods, systems, and media for data migration are provided. In some embodiments, the systems may include: at least one computer-readable storage medium including a set of instructions for migrating data records; and at least one processor in communication with the computer-readable storage medium, wherein when executing the set of instructions, the at least one processor is directed to: query data in a data storage system comprising a plurality of slave nodes; determine, from a plurality of data records in the slave nodes, at least one candidate data record that satisfies a first condition; identify, from the slave nodes, at least one candidate slave node that satisfies a second condition; and in response to determining that the number of the at least one candidate slave node is not less than a threshold value, migrate the candidate data record to a target slave node.

Abstract: The present technology relates to a memory controller capable of shortening a time required for a read operation by storing a map segment output based on a result of counting the number of times a map entry is called in a host. The memory controller controlling a memory device includes a central processing device configured to receive a read request from a host and perform an operation for outputting data corresponding to the read request to the host, and a flash translation layer configured to search for a map entry indicating a mapping relationship between a logical block address and a physical block address by receiving the logical block address corresponding to the read request from the central processing device, and store a read count table based on a result of searching the map entry.

Abstract: Methods, systems, and devices for transaction management based on metadata are described. A host device may transmit a read command to a memory device. Based on the read command, the host device may receive a set of data from the memory device. The host device may also receive metadata associated with the set of data. Based on the metadata, the host device may determine whether the set of data is the data requested by the read command, data requested by a previous read command, or data unrequested by the host device, or some combination. If the set of data is the data requested by the read command or a previous read command, the host device may process the set of data accordingly. If the set of data is data unrequested by the host device, the host device may discard the set of data and retransmit the read command.

Abstract: Methods, systems, and devices for prefetch signaling in a memory system or sub-system are described. A memory device (e.g., a local memory controller of memory device) of a main memory may transmit a prefetch indicator indicating a size of prefetch data associated with a first set of data requested by an interface controller. The size of the prefetch data may be equal to or different than the size of the first set of data. The main memory may, in some examples, store the size of prefetch data along with the first set of data. The memory device may transmit the prefetch indicator (e.g., an indicator signal) to the interface controller using a pin compatible with an industry standard or specification and/or a separate pin configured for transmitting command or control information. The memory device may transmit the prefetch indicator while the first set of data is being transmitted.

Abstract: Systems and methods are disclosed including a processing device operatively coupled to memory device. The processing device performs operations comprising receiving a memory access command specifying a logical address; determining a physical address associated with the logical address; determining a portion of the memory device that is referenced by the physical address; determine an endurance factor associated with the portion; and increasing, by a value derived from the endurance factor, a media management metric associated with a management unit of the memory device, wherein the management unit is referenced by the physical address.

Abstract: A storage system erases blocks of memory prior to writing data to the blocks. Instead of erasing the blocks at the time the write operations are executed, the storage system pre-erases the blocks, which can improve performance. However, because program failure errors can occur if the blocks sit empty for a relatively-long period of time prior to programming, the storage system pre-erases the blocks upon a prediction that a host will send sequential write commands to the storage system that will use the blocks. Additionally or alternatively, the storage system can pre-erase a block upon determining that the number of write commands in a command queue in the storage system is above a threshold that represents a number of write commands needed to fill the block with data.

Abstract: A digital system includes a non-volatile calculating register having a set of latches configured to perform a calculation. A set of non-volatile storage cells is coupled to the set of latches. Access detection logic is coupled to the calculating register and is operable to initiate a calculation of a next value by the calculating register each time the calculating register is accessed by an accessing module. The access detection logic is operable to cause the next value to be stored in the set of non-volatile storage cells at the completion of the calculation as an atomic transaction. After a power loss or other restore event, the contents of the calculating register may be restored from the non-volatile storage cells.

Abstract: The problem to be solved is to seek an alternative to known addressing methods which provides the same or similar effects or is more secure. Solution The problem is solved by a method (40) of addressing memory in a data-processing apparatus (10) comprising, when a central processing unit (11), while performing a task (31, 32, 33, 34) of the apparatus (10), executes an instruction involving a pointer (59) into a segment (s, r, d, h, f, o, i, c) of the memory: decoding the instruction by means of an instruction decoder (12), generating a virtual address (45) within the memory by means of a safe pointer operator (41) operating on the pointer (59), augmenting the virtual address (45) by an identifier (43) of the task (31, 32, 33, 34) and an identifier (44) of the segment (s, r, d, h, f, o, i, c), said identifiers (43, 44) being hardware-controlled (42), and, based on the augmented address (45), dereferencing the pointer (59) via a memory management unit (13).

Abstract: A data processing system includes first memory system including a first nonvolatile memory device; a second memory system including a second nonvolatile memory device; and a master system including a third nonvolatile memory device. The master system classifies any one of the first memory system and the second memory system as a first slave system and the other as a second slave system depending on a predetermined reference, wherein the master system is coupled to a host, and includes a write buffer for temporarily storing a plurality of write data, and wherein the master system classifies the write data, into first write data grouped into a transaction and second write data which are not grouped into the transaction, stores the second write data in the third nonvolatile memory device, and stores the first write data in the first nonvolatile memory device or the second nonvolatile memory device.

Abstract: In an example, an apparatus comprises a plurality of compute engines; and logic, at least partially including hardware logic, to detect a cache line conflict in a last-level cache (LLC) communicatively coupled to the plurality of compute engines; and implement context-based eviction policy to determine a cache way in the cache to evict in order to resolve the cache line conflict. Other embodiments are also disclosed and claimed.

Abstract: According to one embodiment, a storage device includes a nonvolatile memory and a controller. The controller is configured to select a first mode as a write mode to write data from the host to the nonvolatile memory when the controller receives a first instruction from the host. In the first mode, n-bit data is written into a memory cell in a first area of the nonvolatile memory, n being a positive integer more than or equal to 1. The controller is configured to select another mode different from the first mode as the write mode when the controller receives a second instruction from the host.

Abstract: Provided herein is a memory device and a storage device including the same. The memory device includes an input/output circuit configured to receive a command, an address, and data from a memory controller. The memory device also includes control logic configured to control a peripheral circuit of the memory device so that an operation of storing the data in a memory cell of the memory device is performed based on the command and the address received from the input/output circuit. The input/output circuit includes a queue layer configured to temporarily store the command and the address and to output the command and the address to the control logic based on at least one of a rising edge and a falling edge of a write enable signal received by the memory device from the memory controller.

Abstract: A storage device is configured to manage a plurality of nonvolatile memories with a plurality of physical streams. An operation method of the storage device includes receiving an input/output request from an external host device, determining a 0-th virtual stream identifier, extracting a 0-th representative value from a 0-th virtual stream feature, extracting a first and second representative values corresponding to first and second physical streams, calculating distance information including first and second similarities between the 0-th virtual stream and each of the first and second physical streams, based on the extracted representative values, assigning one of the plurality of physical streams to the 0-th virtual stream, based on the distance information, and performing an operation corresponding to the input/output request, at the assigned physical stream, and the extracting and the calculating are performed by using machine learning model.

Abstract: The present invention provides a memory controller configured to access a plurality of channels, wherein each of the channels includes a plurality flash memory chips, and the memory controller includes a flash translation layer and a plurality of control modules. The flash translation layer is configured to generate commands with corresponding physical addresses of at least one of the channels. The plurality of control modules are connected to the plurality of channels, respectively, and each of the control modules operates independently to receive the corresponding command with the corresponding physical address from the flash translation layer, to access the flash memory chips within the corresponding channels.

Abstract: In a storage system such as a SAN, NAS, or storage array that implements hierarchical performance tiers based rated drive access latency, on-drive compression is used on data stored on a first tier and off-drive compression is used on data stored on a second tier. Off-drive compression is more processor intensive and may introduce some data access latency but reduces storage requirements. On-drive compression is performed at or near line speed but generally yields lower size reduction ratios than off-drive compression. On-drive compression may be implemented at a higher performance tier whereas off-drive compression may be implemented at a lower performance tier. Further, space saving realized from on-drive compression may be applied to over-provisioning.