Abstract: A method of forming an electrical contact between interconnection layers located at different layer levels includes the steps of forming a contact hole in an interlayer insulating film, and forming a metallic intermediate layer on an exposed surface portion of a first conductive interconnection layer and the interlayer insulating film. Then, a portion of said metallic intermediate layer exposed through said contact hole and an oxide film formed on said surface portion of the first conductive interconnection layer are eliminated by an etching process. This process is carried out in a vacuum. After that, in the vacuum, a second conductive interconnection layer is formed in said contact hole and formed on said interlayer insulating film so that an electrical contact between said first and second conductive interconnection layers are formed.

Abstract: A method of manufacturing a semiconductor device in which an element is flattened by improving a technique of forming an interlayer insulating film. A thick insulating film having a film thickness necessary for a convexo-concave pattern to be flattened is deposited on a semiconductor substrate comprising the convexo-concave pattern of an element, a wiring and the like. Then, the thick insulating film is etched until it becomes a predetermined film thickness to form an interlayer insulating film having a predetermined film thickness from said thick insulating film. At this time, since acid and water are attached on the surface of the interlayer insulating film, a new film is formed on the surface of the interlayer insulating film to cover this water and acid. Then, a resist pattern having a desired configuration is formed on this new film. A contact hole is formed on the interlayer insulating film using this resist pattern.

Abstract: A method of forming a conductive via plug or an interconnect line, or both, of solid ductile metal within an integrated circuit using plastic deformation of the solid metal, and a dry polishing method of removing excess metal from a metal layer atop an underlying layer on a semiconductor substrate wafer. The process begins with a wafer having a dielectric layer, the upper surface of which has been planarized. If both conductive via plugs and interconnect lines are both required within the circuit, a first masking step defines the interconnect lines. A first etch creates channels in the interconnect line locations. A second masking step defines the vias. A second etch creates the vias which pass through the dielectric layer to conductive regions below where contact is to be made. A layer of solid ductile metal is then deposited on top of the dielectric layer.

Abstract: This invention comprehends a multilevel electrically conductive interconnect for an integrated circuit wherein an inventive feature of the interconnect is the intermediate dual dielectric layer between the non-contacting portions of the surrounding metal conductors. The dual dielectric layer consists of a first dielectric layer and a second dielectric layer preferably formed from a polyimide material. The dual dielectric layer provides a significant improvement in defect density and a substantially planarized surface for the deposition of the top conductor, thereby improving the reliability and integrity of the electrical interconnection and integrated circuit.

Abstract: An improved structure and process for contacting and interconnecting semiconductor devices within a VLSI integrated circuit are described. The structure includes several regions which cooperate to provide (1) contacts of low electrical resistance to semiconductor device terminals, (2) barriers to unwanted metallurgic reactions, (3) strong bonds between major regions of the structure, (4) overall mechanical strength, (5) a primary current path of low electrical resistance, (6) a secondary current path in parallel with the primary current path, and (7) circuit bond pads for use in making electrical connections to the VLSI circuit. Because of the structure's mechanical strength, semiconductor devices may be placed beneath circuit bond pads. The inventive process facilitates accurate control of the composition and thickness of each of the several regions within the material structure.

Abstract: A planar surface is produced in integrated circuit processing by patterning a bilevel structure of a conductor and a sacrificial layer followed by directional deposition of a dielectric and lift off of the sacrificial layer. An additional dielectric layer may now be deposited if desired.

Abstract: A method for improving step coverage of metallization layers of an aluminum alloy on an integrated circuit involves use of a deposited layer of molybdenum as an anti-reflective coating to increase the efficient use of laser energy for planarization purposes where the underlying aluminum alloy covers a step, such as an open contact hole or via.

Abstract: A semiconductor device having a bump electrode on a semiconductor substrate above an electrode pad and metal film. The shape of the bump electrode is composed of a cubical portion and a skirt extending outward from the bottom of the cubical portion. In manufacturing such a semiconductor device, a dry film is used which is laminated on the metal film under a certain laminating condition and formed with an opening. A bump material is formed as a deposit on the metal film within the opening, through electrolytic plating. The deposit has the cubical portion corresponding in shape to the opening, and the skirt extending outward into a space between the dry film and the metal film, from the bottom of the cubical portion. The metal film is etched out using the deposit as a mask to thereby make the deposit as a bump electrode of the semiconductor device.

Abstract: In the manufacture of integrated-circuit devices, patterned features are made on a substrate by etching a deposited layer. The pattern comprises features which are closely spaced, as well as others which are more isolated. Etching is in approximate conformance with a lithographically defined resist pattern which in turn is in approximate conformance with a desired pattern. A processing parameter such as, e.g., resist layer thickness is chosen such that an etched pattern is obtained which approximates a desired pattern more closely than a lithographically defined resist pattern.

Abstract: A method for forming lower levels of metal in multilevel interconnects involves initial formation of a poly-metal dielectric layer having grooves and contact holes, subsequent deposition of a covering layer of metal, masking of the covering layer and etching to produce protruding pillars, and addition of an intermetal dielectric layer surrounding the pillars. The process steps produce a metal level having integral studs or posts, conduction strips and contacts.

Abstract: A method is provided for forming multiple layers of interconnection adjacent a planar surface. A first insulator layer is formed adjacent the selected planar surface. A first conductor layer is formed adjacent the first insulator layer. A second insulator is formed adjacent the first conductor layer. A first cavity and a second cavity are formed, each having sidewalls extending through said second insulator layer and said first conductor layer. The first cavity is formed wider than the second cavity. A third insulator layer is conformally deposited adjacent the second insulator layer, such that sidewall insulators are deposited on sidewalls of the first cavity and such that the second cavity is substantially filled with insulator. An etch is performed through the first cavity to expose a portion of the planar surface. A second conductor layer is conformally deposited adjacent third insulator layer such that second conductor layer extends through the first cavity to contact the planar surface.

Abstract: A dielectric layer of first interconnection for electronic semiconductor devices, specifically CMOS circuits, comprises a first thickness of tetraethylorthosilicate which is overlaid by a layer of self-planarizing siloxane. That layer provides a surface structure which is permissive of the subsequent conventional masking and electric contact attaching steps.

Abstract: The disclosed invention is a method for fabricating a multi-layer semiconductor device using selective planarization. In accordance with one embodiment of the invention, conductive members are formed on a substrate and a first insulating layer is deposited onto the substrate and the conductive members. A second insulating layer, which has a lower flow temperature than the flow temperature of the first layer, is deposited onto the first layer. A photoresist mask is patterned and developed to form a window which exposes an area between the conductive members. The device is preferentially etched such that only the exposed areas of the second insulating layer are removed, leaving the first insulating layer intact. An anisotropic etch is used to remove portions of the first insulating layer, leaving spacers along the edges of the conductive members. The photoresist mask is removed and a heating step is performed which flows the remaining portions of the second insulating layer, but not the first layer.

Abstract: An alternating cyclic (A.C.) method for selectively depositing single element semiconductor materials, on the surface of a substrate without depositing the material on an adjacent mask layer. A gas of a reducible compound of the material and a reducing gas, preferably hydrogen, are simultaneously flowed through a reaction chamber to deposit the material on the substrate surface and to a lesser extent on the mask layer. Then, the flow of reducing gas is interrupted to cause the reducible compound gas to etch the material which forms on the mask layer in a disproportionation reaction. The deposition and etch steps are repeated in an alternating cyclic fashion until the requisite thickness is deposited. The process may take place in a single reaction chamber, using only the reducible compound gas and pulsed flow of the reducing gas.

Abstract: A process for manufacturing a combination and protection diode on a substrate comprising a first, highly doped, thick N-type layer (40) and a second N-type, low doped, layer (10), comprises the following successive steps: implanting in a small surface area N-type dopants (12), carrying out a first annealing process, implanting in a second area including and surrounding the first area N-type dopants (22), carrying out a second annealing process, inplanting in a third area including the first area and at least one portion of the second area P-type dopants (32), and carrying out a third annealing process.

Abstract: A method of forming digit lines on a semiconductor wafer having integrated circuits comprises the following consecutive steps:selectively processing the wafer to produce a desired array of dynamic random access memory cells having associated word lines and exposed active areas, the word lines being defined by electrically conductive regions comprised of a polysilicon/high conductive material sandwich structure and having side and top electrically insulated regions comprised of oxide;providing a layer of doped epitaxial monocrystalline silicon atop exposed active areas to a height which is below the uppermost portions of the electrically insulated regions atop the word lines, and above the height of the uppermost portions of the word line electrically conductive regions;providing a layer of electrically insulating oxide atop the wafer, the electrically insulating layer having a lowest point which is higher than the height of the doped epitaxial silicon layer;planarizing the electrically insulating layer by rem

Abstract: Disclosed is here a semicondutor integrated circuit device and a method of manufacturing the same in which bipolar transistors and MISFETs are formed on a semiconductor substrate. Emitter and base electrodes of the bipolar transistors and gate, source, and drain electrodes of the MISFETs are constituted with the same polycrystalline layer, thereby realizing a high integration and a high-speed operation of a Bi-CMOS device.

Abstract: An integrated circuit is made by a technique that provides a planar dielectric over gate, source, and drain regions without over-etching of the gate contact region, In the inventive process, the contact windows are etched in the conformal dielectric prior to the planarization step, so that the etch thickness is the same for the gate as for the source/drain windows. Then, a sacrificial planarizing polymer (e.g., a photoresist) is deposited to cover the conformal dielectric and fill the etched windows. Finally, a planarizing etch-back is performed, and the polymer is removed from the contact windows. A planarized dielectric is achieved without excessive etching of the gate windows.

Abstract: The invention provides a method for patterning a submicron opening in a layer of semiconductor material. The method comprises use of conventional photolithography to position a sidewall spacer in a predetermined location on a semiconductor device. A layer of cobalt is selectively reacted with an underlying layer to form an image reversal layer which functions as a hard mask. The submicron features are then transferred into the underlying layer of semiconducting material by etching.

Abstract: An improved process for preparing selective deposition of conductive metals on disilicide encroachment barriers allows the construction of integrated circuit components wherein the metal/disilicide interface is substantially free of O and/or F contamination. The level of interfacial oxygen and/or fluorine contamination in the selective W deposition on the TiSi.sub.2 was substantially reduced or eliminated by first forming a C49 TiSi.sub.2 phase on a substrate, selectively depositing W on the C49 TiSi.sub.2 phase and thereafter annealing at a (minimum) temperature sufficient to convert the high resistivity phase C49 TiSi.sub.2 to the low resistivity phase C54 TiSi.sub.2.