Abstract: A heterogeneous device comprises a substrate and a plurality of heterogeneous circuit devices defined in the substrate. In embodiments, a plurality of heterogeneous circuit devices are integrated by successively masking and ion implanting the substrate. The heterogeneous device may further comprise at least one microelectromechanical system-based element and/or at least one photodiode. In embodiments, the heterogeneous circuit devices comprise at least one CMOS transistor and at least one DMOS transistor. In embodiments, the substrate comprises a layer of silicon or a layer of p-type silicon. In other embodiments, the substrate comprises a silicon-on-insulator wafer comprising a single-crystal-silicon layer or a single-crystal-P-silicon layer, a substrate and an insulator layer therebetween.

Abstract: A thin film transistor substrate and a fabricating method thereof that are capable of improving an aperture ratio. A gate electrode on that substrate has an inclined head and a concave neck.

Abstract: A laser annealing method for obtaining a crystalline semiconductor film having a large grain size is provided. Laser light is irradiated to the top surface and the bottom surface of an amorphous semiconductor film when crystallizing the amorphous semiconductor film by laser light irradiation. Furthermore, a relationship of 0<(I0?/I0)<1, or 1<(I0?/I0) is achieved for the ratio (I0/I0?) between the effective energy strength of the laser light when irradiated to the top surface (I0) and the effective energy strength of the laser light when irradiated to the bottom surface (I0?).

Abstract: A memory cell having a bit line contact is provided. The memory cell may be a 6F2 memory cell. The bit line contact may have a contact hole bounded by insulating sidewalls, and the contact hole may be partially or completely filled with a doped polysilicon plug. The doped polysilicon plug may have an upper plug surface profile that is substantially free of concavities or substantially convex. Similarly, a storage node contact may comprise a doped polysilicon plug having an upper plug surface profile that is substantially free of concavities or that is substantially convex. Additionally, a semiconductor device having a conductive contact comprising a polysilicon plug may is provided. The plug may contact a capacitor structure.

Abstract: A method to form a programmable resistor device in an integrated circuit device is achieved. The method comprises depositing a semiconductor layer overlying a substrate. The semiconductor layer is patterned to form a plurality of lines. The lines are electrically parallel between a first terminal and a second terminal. Any of the lines may be blown open by a current forced from the first terminal to the second terminal. A metal-semiconductor alloy is selectively formed overlying a first group of the lines but not overlying a second group of the lines. A method to program the programmable resistor device is described.

Abstract: A substrate processing apparatus and a substrate processing method are provided wherein an oxide film which is thinner than the conventional films can be formed with uniform thickness when forming an oxide film on the front-side surface of a substrate. A substrate processing apparatus (12) for processing a substrate (W) by feeding a processing liquid comprises: a temperature regulator (133) to regulate the temperature of said processing liquid; and a underplate temperature adjuster (115) to adjust the temperature of an underplate (77) which is placed in proximity to the backside surface of said substrate W.

Abstract: A semiconductor device which can enhance adhesiveness between a barrier conductive film and an organic insulating film, and prevent film-fall-off, and the manufacturing technique thereof are provided. After a silicon nitride film is formed on the main surface of semiconductor substrate, an organic insulating film is formed on the silicon nitride film. The organic insulating film is formed of a material having a dielectric constant lower than that of a silicon oxide film. Subsequently, wiring grooves are formed in the silicon nitride film and the organic insulating film by means of a photolithography technique and etching technique. An oxide film is formed by irradiating the organic insulating film with ultraviolet rays by use of excimer lamp. The ultraviolet-ray irradiation is performed in an atmosphere containing oxygen. A tantalum film serving as a barrier conductive film is formed on the organic insulating film with the mediation of the oxide film.

Abstract: The present invention provides a method of manufacturing MEMS devices, comprising the steps of forming MEMS device bodies in a first substrate, defining concave portions around the MEMS device bodies over the first substrate, forming convex portions coincident with the concave portions in a second substrate, fitting the convex portions in the concave portions, respectively, to join the first substrate and the second substrate to each other, thereby forming a third substrate, sticking the third substrate to a UV sheet on the second substrate side, and dicing the third substrate to separate the MEMS device bodies from one another.

Abstract: Gate length is 110 nm±15 nm or shorter (130 nm or shorter in a design rule) or an aspect ratio of an area between adjacent gate electrode structures thereof (ratio of the height of the gate electrode structure to the distance between the gate electrode structures) is 6 or higher. A PSG (HDP-PSG: Phospho Silicate Glass) film containing a conductive impurity is formed as an interlayer insulating film for burying the gate electrode structures at film-formation temperature of 650° C. or lower by a high-density plasma CVD (HDP-CVD) method.

Abstract: A lower electrode may be covered by a protective film to reduce the exposure of the lower electrode to subsequent processing steps or the open environment. As a result, materials that may have advantageous properties as lower electrodes may be utilized despite the fact that they may be sensitive to subsequent processing steps or the open environment.

Abstract: An object of the present invention is to provide an active matrix type display unit having a pixel structure in which a pixel electrode formed in a pixel portion a scanning line (gate line) and a data line are suitably arranged, and high numerical aperture is realized without increasing the number of masks and the number of processes. In this display unit, a first wiring arranged between a semiconductor film and a substrate through a first insulating film is overlapped with this semiconductor film and is used as a light interrupting film. Further, a second insulating film used as a gate insulating film is formed on the semiconductor film. A gate electrode and a second wiring are formed on the second insulating film. The first and second wirings cross each other through the first and second insulating films. A third insulating film is formed as an interlayer insulating film on the second wiring, and a pixel electrode is formed on this third insulating film.

Abstract: The semiconductor device comprises a semiconductor layer 18 formed on an insulation layer 16, a gate electrode 22 formed on the semiconductor layer with a gate insulation film 20 formed therebetween, a source/drain region 24 formed on the semiconductor layer on both sides of the gate electrode, and a semiconductor region 14 buried in the insulation layer 16 in a region below the gate electrode. The surface scattering of the carriers and phonon scattering can be prevented while suppressing the short channel effect. Resultantly the semiconductor device can have high mobility and high speed.

Abstract: The power semiconductor device according to one embodiment of the present invention at least comprises: first pillar layers of the first conductive type and second pillar layers of a second conductive type which constitute a super-junction structure in a device section and which are arranged alternately in a horizontal direction, each of the first and second pillar layers having a column-shaped sectional structure; third pillar layers of the first conductive type and fourth pillar layers of the second conductive type which are adjacent to the super-junction structure of the device section to constitute another super-junction structure thinner in a vertical direction than the super-junction structure of the device section in a device termination section and which are arranged alternately in a horizontal direction, each of the third and fourth pillar layers having a column-shaped sectional structure; an outermost pillar layer which is stacked on one of the third or fourth pillar layers in the super-junction str

Abstract: The present invention relates to a method for fabricating a semiconductor device capable of preventing bridge formation caused by damages to a capacitor oxide structure including a phosphosilicate glass (PSG) layer and a tetraethylorthosilicate (TEOS) layer during a wet cleaning process. The method includes the steps of: forming a PSG layer on a substrate; forming a capping layer on the PSG layer; forming a TEOS layer on the capping layer; selectively etching the TEOS layer, the capping layer and the PSG layer to form a plurality of openings exposing predetermined portions of the substrate; cleaning the openings; forming a conductive layer on the openings; and removing the conductive layer until the TEOS layer is exposed, so that the conductive layer is isolated for each opening.

Abstract: The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.

Abstract: Methods for etching metal nitrides and metal oxides include using ultradilute HF solutions and buffered, low-pH HF solutions containing a minimal amount of the hydrofluoric acid species H2F2. The etchant can be used to selectively remove metal nitride layers relative to doped or undoped oxides, tungsten, polysilicon, and titanium nitride. A method is provided for producing an isolated capacitor, which can be used in a dynamic random access memory cell array, on a substrate using sacrificial layers selectively removed to expose outer surfaces of the bottom electrode.

Abstract: An organic electroluminescent device includes a substrate, a plurality of gate lines on the substrate, a plurality of data lines on the substrate, each of the plurality of data lines crossing the gate lines, a plurality of switching elements and driving elements interconnected on the substrate, and a power line disposed in parallel to the data lines on the substrate, wherein the power line is electrically connected to at least two of the plurality of driving elements.

Abstract: A method of defining a patterned, conductive gate structure for a MOSFET device on a semiconductor substrate includes forming a conductive layer over the semiconductor substrate and forming a capping insulator layer over the conductive layer. An anti-reflective coating (ARC) layer is formed over the capping insulator layer and a patterned photoresist shape is formed on the ARC layer. A first etch procedure using the photoresist shape as an etch mask defines a stack comprised of an ARC shape and a capping insulator shape. A second etch procedure using the stack as an etch mask defines the patterned, conductive gate structure in the conductive layer.

Abstract: A method with a mechanically strained silicon for enhancing the speeds of integrated circuits or devices is disclosed. The method with a mechanically strained silicon for enhancing the speeds of integrated circuits or devices includes the following steps: (a) providing a substrate, (b) fixing the substrate, (c) applying a stress upon the substrate, and (d) inducing a strain in one of a device and a circuit by stressing the substrate.

Abstract: A semiconductor laminate containing a light-emitting layer is etched to reveal a side surface. A reflection surface opposite to the side surface of the semiconductor laminate is provided in one and the same chip as the semiconductor laminate. A groove may be formed in the laminate by a dicing saw, and an outer side surface of the groove may be provided as the reflection surface.