Patents Examined by Laura Menz
  • Patent number: 10249738
    Abstract: A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: April 2, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan
  • Patent number: 10211162
    Abstract: This method for measuring the misalignment between a first and a second etching zone includes: producing a plasmonic antenna including a first and a second element that are separate and each delineate a cavity on one respective side, all of the elements of the plasmonic antenna that are situated on a first side of a separating plane being produced entirely inside the first zone and all of the elements of the plasmonic antenna that are situated on the second side of the separating plane being produced entirely inside the second zone, and after the production of the plasmonic antenna, the method includes: measuring the absorption rate of the plasmonic antenna, and determining the magnitude of the misalignment between the first and second zones on the basis of the measured absorption rate and of a predicted value for this absorption rate in the absence of a misalignment.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: February 19, 2019
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Guido Rademaker, Salim Boutami, Jonathan Pradelles
  • Patent number: 10203369
    Abstract: A test interface board includes an encoder, a signal copier, and a decoder. The encoder digitally encodes test data to generate a modulation signal. The signal copier copies the modulation signal by inductively coupling the modulation signal and outputs at least one copy signal corresponding to the modulation signal. The decoder decodes the modulation signal and the at least one copy signal in order to test at least two semiconductor devices.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: February 12, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joo-sung Yun, Ki-jae Song, Ung-jin Jang, Woon-sup Choi, Jae-hyun Kim
  • Patent number: 10204939
    Abstract: A display substrate, a manufacturing method thereof and a display device are provided. The manufacturing method of the display substrate includes: forming a plurality of display substrate regions and a plurality of connection lines on a mother substrate, wherein each of the display substrate regions includes a plurality of peripheral wirings, and the plurality of peripheral wirings of each of the display substrate regions are electrically connected with each other through at least one of the plurality of connection lines; and cutting the mother substrate according to the plurality of display substrate regions to form a plurality of display substrates, wherein the plurality of peripheral wirings of each of the cut display substrates are disconnected from each other.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: February 12, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Jingang Hao
  • Patent number: 10204998
    Abstract: A heterostructure device includes a channel layer, a barrier layer disposed on the channel layer, and a first electrode and a second electrode disposed on the barrier layer, respectively. The second electrode includes a p-type semiconductor structure and a raised section disposed on the p-type semiconductor structure, the second electrode includes a Schottky contact and an ohmic contact, the Schottky contact is formed between a top surface of the p-type semiconductor structure and a first bottom surface of the raised section, the ohmic contact is formed between a second bottom surface of the raised section and the barrier layer.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: February 12, 2019
    Assignee: EPISTAR CORPORATION
    Inventors: Ya-Yu Yang, Ping-Hao Lin
  • Patent number: 10197259
    Abstract: A system and method for incorporating occupancy-detecting technology into furniture is provided. More particularly, the invention relates to detecting occupancy by a standalone capacitance detection device. The standalone capacitance detection device is configured for integration with any number of furniture items. Further, the detected capacitance may be used to determine commands for controlling a variety of devices associated with the standalone capacitance detection device. Additionally, methods for determining occupancy of a furniture item and a system for monitoring occupancy are described herein.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: February 5, 2019
    Assignee: L&P Property Management Company
    Inventors: Ryan Edward Chacon, Avinash Madadi, William Robert Rohr, Jason B. Turner, Caleb Browning
  • Patent number: 10188050
    Abstract: The present embodiments provide systems, processes and/or methods of controlling irrigation. In some embodiments, methods are provided that receive (4112) water usage information corresponding to a first volumetric water usage at a site location having an irrigation controller (130), wherein the first volumetric water usage corresponds to volumetric water usage from a beginning of a budget period of time to a first time within the budget period of time; determine (4114) automatically whether a volumetric water budget at the site location will be met for the budget period of time based on at least the first volumetric water usage, the volumetric water budget corresponding to a specified volume of water for use during the budget period of time; determine (4116) automatically, in the event the volumetric water budget will not be met, an adjustment to the irrigation by the irrigation controller; and output (4118) signaling to effect the adjustment.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: January 29, 2019
    Assignee: Rain Bird Corporation
    Inventors: Ryan L. Walker, Harvey J. Nickerson, Blake Snider
  • Patent number: 10186901
    Abstract: A method for decentralizing a piece of information pertaining to a power availability situation in a power grid at a particular instant includes ascertaining power availability data in the power grid by a power control center that is associated with the power grid, and generating a piece of power availability information by the power control center at the particular instant. The method also includes transmitting the power availability information from the power control center to at least one data reception system, and processing and/or outputting the power availability information by the data reception system.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: January 22, 2019
    Assignee: Bayerische Motoren Werke Aktiengesellschaft
    Inventor: Peter Rohrauer
  • Patent number: 10186473
    Abstract: An object of the present invention is to provide a power module capable of realizing a superior heat radiation property while satisfying a high insulation property. A power module according to the present invention includes: a conductor plate to which a switching element is connected; a heat radiation plate which is disposed to face the conductor plate; an insulating member which is disposed between the conductor plate and the heat radiation plate; and a conductive intermediate conductor which is disposed in the insulating member in a state of being electrically insulated from the conductor plate and the heat radiation plate, wherein the intermediate conductor has a communication region which communicates between the insulating member disposed on the side of the conductor plate with respect to the intermediate conductor and the insulating member disposed on the side of the heat radiation plate with respect to the intermediate conductor.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: January 22, 2019
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Fusao Hojo, Nobutake Tsuyuno, Toshiaki Ishii, Junpei Kusukawa, Akira Matsushita
  • Patent number: 10163776
    Abstract: Disclosed herein is a capacitive element formed by multilayer wirings, wherein a total capacitance, intralayer capacitance and interlayer capacitance are calculated for a plurality of device structures by changing parameters relating to the multilayer wirings in an integrated circuit, a device structure is identified, from among the plurality of device structures, whose difference in the total capacitance between the device structures is equal to or less than a predetermined level and at least either of whose ratio of the intralayer capacitance to the total capacitance or ratio of the interlayer capacitance to the total capacitance satisfies a predetermined condition, and the parameters of the device structure satisfying the predetermined condition are determined as the parameters of the multilayer wirings.
    Type: Grant
    Filed: January 5, 2010
    Date of Patent: December 25, 2018
    Assignee: Sony Corporation
    Inventors: Kyoko Izuha, Hiroaki Ammo, Yoshiyuki Enomoto
  • Patent number: 10163634
    Abstract: Various patterning methods involved with manufacturing semiconductor device structures are disclosed herein. A method for forming a semiconductor device structure (for example, a conductive line) includes forming a first hard mask layer and a second hard mask layer over a dielectric layer. The first hard mask layer has a first opening, and the second hard mask layer has a first trench connected to the first opening. A filling layer is formed in the first opening, where the filling layer has a second opening and a third opening. The first hard mask layer and the dielectric layer are removed through the second opening and the third opening to form a second trench and a third trench in the dielectric layer. The first hard mask layer, the second hard mask layer, and the filling layer can be removed. A conductive layer is formed in the second trench and the third trench.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yung-Sung Yen, Ken-Hsien Hsieh, Ru-Gun Liu
  • Patent number: 10158043
    Abstract: A method for manufacturing a light-emitting diode (LED) includes plural steps as follows. A first type semiconductor layer is formed. A second type semiconductor layer is formed on the first type semiconductor layer. An impurity is implanted into a first portion of the second type semiconductor layer. The concentration of the impurity present in the first portion of the second type semiconductor layer is greater than the concentration of the impurity present in a second portion of the second type semiconductor layer after the implanting, such that the resistivity of the first portion of the second type semiconductor layer is greater than the resistivity of the second portion of the second type semiconductor layer.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: December 18, 2018
    Assignee: MIKRO MESA TECHNOLGY CO., LTD.
    Inventors: Li-Yi Chen, Pei-Yu Chang, Hsin-Wei Lee, Chun-Yi Chang, Shih-Chyn Lin
  • Patent number: 10157884
    Abstract: A package includes package includes a first package component including a first plurality of electrical connectors at a top surface of the first package component, and a second plurality of electrical connectors longer than the first plurality of electrical connectors at the top surface of the first package component. A first device die is over the first package component and bonded to the first plurality of electrical connectors. A second package component is overlying the first package component and the first device die. The second package component includes a third plurality of electrical connectors at a bottom surface of the second package component. The third plurality of electrical connectors is bonded to the second plurality of electrical connectors. A fourth plurality of electrical connectors is at a bottom surface of the second package. The second and the fourth plurality of electrical connectors comprise non-solder metallic materials.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chen-Shien Chen, Yen-Chang Hu
  • Patent number: 10156907
    Abstract: A device for analyzing the movement of at least one moving element (EM), provided, for at least one moving element, with first means (DET1) for determining the orientation of a moving coordinate frame (Rm) connected in motion to the moving element (EM), with respect to a reference coordinate frame (Rr), including second means (DET2) for determining at least one locus of points (Tx, Ty, Tz) of at least one surface from at least one respective direction of an oriented axis (x, y, z) of the moving coordinate frame (Rm) connected in motion to the moving element (EM) and said surface.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: December 18, 2018
    Assignee: InvenSense, Inc.
    Inventor: Yanis Caritu
  • Patent number: 10147808
    Abstract: Techniques for increasing a source-to-channel tunneling area in TFETs are provided. In one aspect, a method of forming a vertical TFET includes: patterning at least one pair of fins in an undoped semiconductor layer (vertical fin channels) and doped drain layer, filling gaps between the pair of fins with a dielectric; forming gates along outer sides of the pair of fins; partially recessing the dielectric to form a trench in between the pair of fins; forming a doped source layer in the trench overlapping the vertical fin channels. A vertical TFET device formed by the method is also provided, as is a vertical TFET device and method for formation thereof where a positioning of the doped source layer and the gates is reversed.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: December 4, 2018
    Assignee: International Business Machines Corporation
    Inventors: Juntao Li, Kangguo Cheng, Xin Miao, Peng Xu
  • Patent number: 10145968
    Abstract: The present disclosure provides a system and method for efficiently mining multi-threshold measurements acquired using photon counting pixel-array detectors for spectral imaging and diffraction analyses. Images of X-ray intensity as a function of X-ray energy were recorded on a 6 megapixel X-ray photon counting array detector through linear fitting of the measured counts recorded as a function of counting threshold. An analytical model is disclosed for describing the probability density of detected voltage, utilizing fractional photon counting to account for edge/corner effects from voltage plumes that spread across multiple pixels. Three-parameter fits to the model were independently performed for each pixel in the array for X-ray scattering images acquired for 13.5 keV and 15.0 keV X-ray energies. From the established pixel responses, multi-threshold composite images produced from the sum of 13.5 keV and 15.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: December 4, 2018
    Assignee: PURDUE RESEARCH FOUNDATION
    Inventors: Garth Jason Simpson, Ryan Douglas Muir, Nicholas Roman Pogranichniy
  • Patent number: 10139358
    Abstract: In an embodiment, a method comprises fitting a spectroscopic data of a layer in a layered structure to a dielectric function having a real part and an imaginary part; confirming that the dielectric function is physically possible; based on the dielectric function not being physically possible, repeating the fitting the spectroscopic data, or, based on the dielectric function being physically possible, defining an n degree polynomial to the dielectric function; determining a second derivative and a third derivative of the n degree polynomial; equating the second derivative to a first governing equation and the third derivative to a second governing equation and determining a constant of the first governing equation and the second governing equation; and based on the key governing equations, determining one or more of a band gap, a thickness, and a concentration of the layer.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: November 27, 2018
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Lisa F. Edge, Gangadhara R. Muthinti, Shariq Siddiqui
  • Patent number: 10128116
    Abstract: Efficient integrated sequential deposition of alternating layers of dielectric and conductor, for example oxide/metal or metal nitride, e.g., SiO2/TiN, in a single tool, and even in a single process chamber enhances throughput without compromising quality when directly depositing a OMOM stack with many layers. Conductor and dielectric film deposition of a stack of at least 20 conductor/dielectric film pairs in the same processing tool or chamber, without breaking vacuum between the film depositions, such that there is no substantial cross-contamination between the conductor and dielectric film depositions, can be achieved.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: November 13, 2018
    Assignee: LAM RESEARCH CORPORATION
    Inventors: William T. Lee, Bart J. van Schravendijk, David Charles Smith, Michal Danek, Patrick A. Van Cleemput, Ramesh Chandrasekharan
  • Patent number: 10118816
    Abstract: A packaged includes a flip-chip assembly. The flip-chip assembly includes a first semiconductor substrate having at least one integrated semiconductor device, and a second substrate connected to the first substrate. A main surface of the first semiconductor substrate faces and is spaced apart from the second substrate. The packaged semiconductor device further includes a parylene coating covering outer surfaces of the first semiconductor substrate and the second substrate. A first section of the main surface is exposed from the parylene coating.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: November 6, 2018
    Assignee: Infineon Technologies AG
    Inventors: Klaus Elian, Horst Theuss
  • Patent number: 10109676
    Abstract: A magnetic tunnel junction (MTJ) structure includes a fixed layer pattern structure having a perpendicular magnetization direction, a tunnel barrier pattern on the fixed layer pattern structure, a free layer pattern on the tunnel barrier pattern, the free layer pattern having a perpendicular magnetization direction, a first surface magnetism induction pattern on the free layer pattern, the first surface magnetism induction pattern inducing a perpendicular magnetism in a surface of the free layer pattern, a conductive pattern on the first surface magnetism induction pattern, and a ferromagnetic pattern on the conductive pattern.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: October 23, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Hoon Bak, Woo-Jin Kim, Mina Lee, Gwan-Hyeob Koh, Yoon-Jong Song