Abstract: In an operating machine, one example of a method for monitoring operation of operating machinery includes converting an actual sound pattern generated by the machine into an audio signal and digitizing the audio signal to create a real-time acoustic fingerprint unique to the actual sound pattern. A reference database contains a plurality of stored acoustic fingerprints, each stored acoustic fingerprint in the plurality of stored acoustic fingerprints representing a unique sound pattern associated with a particular operating condition. A controller compares the real-time acoustic fingerprint to the stored acoustic fingerprints in the reference database and generates an output in response to detection of a match between the real-time acoustic fingerprint and one of the plurality of stored acoustic fingerprints. One example of the machine is a corruptor machine that converts paper webs into corrugated paperboard sheets.

Abstract: A semiconductor device includes a first vertical field effect transistor (VFET) formed on a substrate, and including a first fin and a first gate formed on the first fin, a second VFET formed on the substrate and connected in parallel with the first VFET, and including a second fin and a second gate formed on the second fin, a third VFET formed on the substrate and including a third fin, the first and second gates being formed on the third fin, and a fourth VFET formed on the substrate and connected in series with the third VFET, and including a fourth fin, the first and second gates being formed on the fourth fin.

Abstract: In an embodiment, a semiconductor structure includes a support substrate comprising a surface adapted to support epitaxial growth of a Group III nitride, one or more epitaxial Group III nitride layers arranged on the surface and supporting a plurality of transistor devices assembled upon the support substrate, and a test structure formed in a Group III nitride layer. The test structure includes a plurality of trenches configured to provide an optical diffraction grating when illuminated by UV light. The trenches have a parameter corresponding to a parameter of a feature of the transistor devices.

Abstract: A trench metal-oxide-semiconductor field effect transistor (MOSFET), in accordance with one embodiment, includes a drain region, a plurality of gate regions disposed above the drain region, a plurality of gate insulator regions each disposed about a periphery of a respective one of the plurality of gate regions, a plurality of source regions disposed in recessed mesas between the plurality of gate insulator regions, a plurality of body regions disposed in recessed mesas between the plurality of gate insulator regions and between the plurality of source regions and the drain region.

Abstract: A field emission transistor includes a gate, a fold over emitter, and fold over collector. The emitter and the collector are separated from the gate by a void and are separated from a gate contact by gate contact dielectric. The void may be a vacuum, ambient air, or a gas. Respective ends of the emitter and the collector are separated by a gap. Electrons are drawn across gap from the emitter to the collector by an electrostatic field created when a voltage is applied to the gate. The emitter and collector include a first conductive portion substantially parallel with gate and a second conductive portion substantially perpendicular with gate. The second conductive portion may be formed by bending a segment of the first conductive portion. The second conductive portion is folded inward from the first conductive portion towards the gate. Respective second conductive portions are generally aligned.

Abstract: A method includes forming a first plurality of redistribution lines, forming a first metal post over and electrically connected to the first plurality of redistribution lines, and bonding a first device die to the first plurality of redistribution lines. The first metal post and the first device die are encapsulated in a first encapsulating material. The first encapsulating material is then planarized. The method further includes forming a second metal post over and electrically connected to the first metal post, attaching a second device die to the first encapsulating material through an adhesive film, encapsulating the second metal post and the second device die in a second encapsulating material, planarizing the second encapsulating material, and forming a second plurality of redistributions over and electrically coupling to the second metal post and the second device die.

Abstract: A display device according to one or more embodiments includes a display panel configured to display an image, a window substrate above the display panel, and including a display area configured to transmit the image therethrough, and a non-display area around the display area, a first adhesive layer between the display panel and the window substrate, and a decoration film above an upper surface of the window substrate. The decoration film includes a base film and a printing layer at a first surface of the base film.

Abstract: It is an object to provide a transistor having a new multigate structure in which operating characteristics and reliability are improved. In a transistor having a multigate structure, which includes two gate electrodes electrically connected to each other and a semiconductor layer including two channel regions connected in series formed between a source region and a drain region, and a high concentration impurity region is formed between the two channel regions; the channel length of the channel region adjacent to the source region is longer than the channel length of the channel region adjacent to the drain region.

Abstract: A detachable hazard detection device includes a protective covering configured to detachably couple to an article. A plurality of proximity sensors are coupled to the protective covering. Each of the plurality of proximity sensors is configured to gather proximity information. Electronics are embedded in the protective covering, and the electronics include a controller coupled to the plurality of proximity sensors. The controller is configured to determine a proximity of the article to an object based on the proximity information. The controller is further configured to initiate a notification based on the proximity.

Abstract: A method of forming a resistive memory cell, e.g., a CBRAM or ReRAM, may include forming a bottom electrode layer, oxidizing an exposed region of the bottom electrode layer to form an oxide region, removing a region of the bottom electrode layer proximate the oxide region, thereby forming a bottom electrode having a pointed tip region adjacent the oxide region, and forming an electrolyte region and top electrode over at least a portion of the bottom electrode and oxide region, such that the electrolyte region is arranged between the pointed tip region of the bottom electrode and the top electrode, and provides a path for conductive filament or vacancy chain formation from the pointed tip region of the bottom electrode to the top electrode when a voltage bias is applied to the memory cell. A memory cell and memory cell array formed by such method are also disclosed.

Abstract: A display panel including an EL panel unit, a CF panel unit, and a sealing resin layer. In the EL panel, a surface of a sealing layer has a non-flat surface as a whole in a Z-axis direction, with recess portions at light-emitting areas corresponding to regions between banks and protrusion portions at non-light-emitting areas corresponding to tops of the banks. D2<0.90×D1 and S>{(0.90×D1)?D2}×W are satisfied, where D1 (D1(R), D1(G), D1(B)) denotes a distance between the EL panel unit and the CF panel unit at a first recess portion, D2 denotes a distance between the EL panel unit and the CF panel unit at a protrusion portion, W denotes a width of a top of the protrusion portion, and S denotes a cross-sectional area of a second recess portion.

Abstract: A semiconductor device includes a fin structure comprising a cylindrical shape and including a recess formed in an upper surface of the fin structure, an inner gate formed inside the fin structure, an outer gate formed outside the fin structure, and a conductor formed in the recess and connecting the inner and outer gates.

Abstract: A semiconductor device includes a semiconductor chip substrate with a chip region and a scribe lane region, center and boundary pads respectively provided on the chip and scribe lane regions, a lower insulating structure provided on the chip region and the scribe lane region, a first conductive pattern including a contact portion, a conductive line portion, and a bonding pad portion, and an upper insulating structure defining first and second openings formed on the bonding pad portion and the boundary pad. The lower insulating structure includes a plurality of lower insulating layers, which are sequentially stacked on the substrate, and each of which is a silicon-containing inorganic layer.

Abstract: According to one embodiment, a semiconductor device includes first and second gate electrodes, a semiconductor layer, an output electrode, and an insulating layer. The semiconductor layer includes first source and drain areas, a first channel area facing the first gate electrode, second source and drain areas, and a second channel area facing the second gate electrode. The output electrode outputs voltage produced in the first and second drain areas. In the semiconductor device, the first drain area is in contact with the second drain area. The insulating layer includes a hole portion communicating with one of the first and second drain areas. The output electrode is in contact with one of the first and second drain areas via the hole portion.

Abstract: Provided is an organic light-emitting display apparatus and a method of repairing the same. The organic light-emitting display apparatus includes: an emission device comprising a plurality of sub-emission devices; an emission pixel circuit configured to supply a driving current to the emission device; a dummy pixel circuit configured to supply the driving current to the emission device; and a repair line coupling the emission device to the dummy pixel circuit, wherein the emission device is configured to receive the driving current from the emission pixel circuit or the dummy pixel circuit.

Abstract: A semiconductor package includes a package substrate. A first semiconductor chip is mounted on the package substrate. The first semiconductor chip includes a first chip region and first chip pads formed on a top surface of the first chip region. A second semiconductor chip is mounted on the package substrate. The second semiconductor chip includes a second chip region and second chip pads formed on a top surface of the second chip region. A boundary region having a groove divides the first chip region and the second chip region. The first chip region, the second chip region and the boundary region share a semiconductor substrate of a one-body type.

Abstract: A plate varactor includes a dielectric substrate and a first electrode embedded in a surface of the substrate. A capacitor dielectric layer is disposed over the first electrode, and a layer of graphene is formed over the dielectric layer to contribute a quantum capacitance component to the dielectric layer. An upper electrode is formed on the layer of graphene. Other embodiments and methods for fabrication are also included.

Abstract: A semiconductor FET provides a resonant gate and source and drain electrodes, wherein the resonant gate is electromagnetically resonant at one or more predetermined frequencies.

Abstract: A semiconductor device includes a semiconductor pattern on a semiconductor substrate, a three-dimensional memory array on the semiconductor pattern, and a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate. The peripheral interconnection structure includes an upper interconnection structure on a lower interconnection structure. The upper interconnection structure includes an upper interconnection and an upper barrier layer. The lower interconnection structure includes a lower interconnection and a lower barrier layer. The upper barrier layer is under a bottom surface of the upper interconnection and does not cover side surfaces of the upper interconnection. The lower barrier layer is under a bottom surface of the lower interconnection and covers side surfaces of the lower interconnection.

Abstract: A plate, a transducer, a method for making a transducer, and a method for operating a transducer are disclosed. An embodiment comprises a plate comprising a first material layer comprising a first stress, a second material layer arranged beneath the first material layer, the second material layer comprising a second stress, an opening arranged in the first material layer and the second material layer, and an extension extending into opening, wherein the extension comprises a portion of the first material layer and a portion of the second material layer, and wherein the extension is curved away from a top surface of the plate based on a difference in the first stress and the second stress.