Abstract: In a method of manufacturing a semiconductor device, first to third active fins are formed on a substrate. Each of the first to third active fins extends in a first direction, and the second active fin, the first active fin, and the third active fin are disposed in this order in a second direction crossing the first direction. The second active fin is removed using a first etching mask covering the first and third active fins. The third active fin is removed using a second etching mask covering the first active fin and a portion of the substrate from which the second active fin is removed. A first gate structure is formed on the first active fin. A first source/drain layer is formed on a portion of the first active fin adjacent the first gate structure.

Abstract: A magnetic tunnel junction (MTJ) structure includes a fixed layer pattern structure having a perpendicular magnetization direction, a tunnel barrier pattern on the fixed layer pattern structure, a free layer pattern on the tunnel barrier pattern, the free layer pattern having a perpendicular magnetization direction, a first surface magnetism induction pattern on the free layer pattern, the first surface magnetism induction pattern inducing a perpendicular magnetism in a surface of the free layer pattern, a conductive pattern on the first surface magnetism induction pattern, and a ferromagnetic pattern on the conductive pattern.

Abstract: A transistor based on topological insulators is provided. In an embodiment a topological insulator is used to form both the channel as well as the source/drain regions, wherein the channel has a first thickness such that the topological insulator material has properties of a semiconductor material and the source/drain regions have a second thickness such that the topological insulator has properties of a conductive material.

Abstract: An array substrate, a manufacturing method thereof and a display device are provided. The array substrate includes: a base substrate; a thin-film transistor and a first conductive layer formed on the base substrate; and a passivation layer formed on the TFT and the first conductive layer. The TFT includes a source electrode and a drain electrode; the first conductive layer is arranged in the same layer with the source electrode and the drain electrode; a second conductive layer is disposed on a side of the first conductive layer opposite to the passivation layer; the passivation layer is provided with a through hole penetrating therethrough; and an orthographic projection of the through hole on the base substrate falls within an orthographic projection of the first conductive layer on the base substrate and falls within an orthographic projection of the second conductive layer on the base substrate.

Abstract: It is an object to provide a transistor having a new multigate structure in which operating characteristics and reliability are improved. In a transistor having a multigate structure, which includes two gate electrodes electrically connected to each other and a semiconductor layer including two channel regions connected in series formed between a source region and a drain region, and a high concentration impurity region is formed between the two channel regions; the channel length of the channel region adjacent to the source region is longer than the channel length of the channel region adjacent to the drain region.

Abstract: An integrated circuit structure includes a semiconductor substrate; a diode; and a phase change element over and electrically connected to the diode. The diode includes a first doped semiconductor region of a first conductivity type, wherein the first doped semiconductor region is embedded in the semiconductor substrate; and a second doped semiconductor region over and adjoining the first doped semiconductor region, wherein the second doped semiconductor region is of a second conductivity type opposite the first conductivity type.

Abstract: A switch circuit includes a first MOS transistor and a second MOS transistor of a same conductivity type connected in parallel between a first terminal and a second terminal of the switch circuit, the first and second MOS transistors having respective gate terminals coupled to the control terminal to receive a control signal to turn the first and second MOS transistors on or off. The first MOS transistor is characterized by a first reverse gate-to-drain capacitance (Crss) and the second MOS transistor is characterized by a second Crss that is greater than the first Crss.

Abstract: Provided is a monolithic integration of resistive memory with complementary metal oxide semiconductor using integrated circuit foundry processes. A memory device is provided that includes a substrate comprising one or more complementary metal-oxide semiconductor devices, a first insulator layer formed on the substrate; and a monolithic stack. The monolithic stack includes multiple layers fabricated as part of a monolithic process over the first insulator layer. The multiple layers include a first metal layer, a second insulator layer, and a second metal layer. A resistive memory device structure is formed within the second insulator layer and within a thermal budget of the one or more complementary metal-oxide semiconductor devices. The resistive memory device structure is implemented as a pillar device or as a via device. Further, the first metal layer is coupled to the second metal layer.

Abstract: The method includes steps for improving gate cut isolation region critical dimension (CD) control. Prior to replacement metal gate (RMG) formation, a first sacrificial gate adjacent to first and second channel regions and made of a first sacrificial material (e.g., polysilicon or amorphous silicon) is replaced with a second sacrificial gate made of a second sacrificial material (e.g., amorphous carbon) that is more selectively and anisotropically etchable. A cut is made, dividing the second sacrificial gate into first and second sections, and the cut is then filled with a dielectric to form the gate cut isolation region. The second sacrificial material ensures that, when an opening in a mask pattern used to form the cut extends over a gate sidewall spacer and interlayer dielectric (ILD) material, recesses are not form within the spacer or ILD. Thus, the CD of the isolation region can be controlled.

Abstract: Systems, methods, and devices for predicting pump performance in a downhole tool are provided. A pump performance predictor may receive inputs and generate outputs that predict the performance of a pump of a pumpout module of a downhole tool. The pump performance predictor may calculate and output a set of first predictions that include, for example, the minimum alternator voltage of a power module used to power the electronics of the pumpout module, the maximum pump flowrate, the pumpout performance, and the achievable formation mobility. The pump performance predictor may also calculate and output a set of second predictions that may include, for example, a pump volume efficiency, a pressure profile in a flowline, the number of strokes to fill a sampling bottle, and the time to fill the sampling bottle.

Abstract: A method of forming an electrical device that includes forming a first level including an array of metal lines, wherein an air gap is positioned between the adjacent metal lines. A second level is formed including at least one dielectric layer atop the first level. A plurality of trench structures is formed in the at least on dielectric layer. At least one of the plurality of trench structures opens the air gap. A conductive material is formed within the trenches. The conductive material deposited in the open air gap provides a vertical fuse.

Abstract: During formation of a trench silicide contact, a sacrificial layer is incorporated into the trench directly over source/drain junctions prior to metallization of the trench. Selective removal of the sacrificial layer widens the trench proximate to the source/drain junctions, increasing the contact area and correspondingly decreasing the contact resistance between the source/drain junctions and a silicide layer.

Abstract: A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a vertical direction with respect to a top surface of the substrate, a plurality of non-metal gate patterns surrounding the channels and being stacked on top of each other and spaced apart from each other along the vertical direction, and a plurality of metal gate patterns stacked on top of each other. The metal gate patterns are spaced apart from each other along the vertical direction. Each of the metal gate patterns surrounds a corresponding one of the non-metal gate patterns.

Abstract: A method of fabricating a semiconductor structure includes providing an engineered substrate including a polycrystalline substrate, a barrier layer encapsulating the polycrystalline substrate, and a bonding layer coupled to the barrier layer. The method further includes forming a first silicon layer coupled to the bonding layer, forming a dielectric layer coupled to the first silicon layer, forming a second silicon layer coupled to the dielectric layer, forming a GaN layer coupled to the second silicon layer, forming a GaN based device coupled to the GaN layer, removing the engineered substrate to expose a back surface of the first silicon layer, forming a silicon based device coupled to the back surface of the first silicon layer, forming a via from the back surface of the first silicon layer, filling the via with a conducting material, and interconnecting the GaN based device and the silicon based device through the via.

Abstract: A micro-LED, ?LED, comprising: a substantially parabolic mesa structure; a light emitting source within the mesa structure; and a primary emission surface on a side of the device opposed to a top of the mesa structure; wherein the mesa structure has an aspect ratio, defined by (H2*H2)/Ac, of less than 0.5, and the ?LED further comprises a reflective surface located in a region from the light emitting source to the primary emission surface, wherein the reflective surface has a roughness, Ra, less than 500 nm.

Abstract: In a solid-state imaging device including a plurality of pixels each pixel including a plurality of photodiodes, it is prevented that an incidence angle of incident light on the solid-state imaging device becomes large in a pixel in an end of the solid-state imaging device, causing a difference in output between the two photodiodes in the pixel, and thus autofocus detection accuracy is deteriorated. Photodiodes extending in a longitudinal direction of a pixel allay section are provided in each pixel. The photodiodes in the pixel are arranged in a direction orthogonal to the longitudinal direction of the pixel allay section.

Abstract: This disclosure is directed to a system and method for detecting a surface of a substrate within a scanner.

Abstract: A method of sealing a workpiece comprising forming an inorganic film over a surface of a first substrate, arranging a workpiece to be protected between the first substrate and a second substrate wherein the inorganic film is in contact with the second substrate; and sealing the workpiece between the first and second substrates as a function of the composition of impurities in the first or second substrates and as a function of the composition of the inorganic film by locally heating the inorganic film with a predetermined laser radiation wavelength. The inorganic film, the first substrate, or the second substrate can be transmissive at approximately 420 nm to approximately 750 nm.

Abstract: A semiconductor device includes a first insulating interlayer on a substrate, metal lines in the first insulating interlayer, a first air gap between the metal lines in a first region of the substrate and a second air gap between the first insulating interlayer and at least one of the metal lines in a second region of the substrate, a liner layer covering top surfaces and side walls of the metal lines and a top surface and a side wall of the first insulating interlayer, adjacent to the first and second air gaps, and a second insulating interlayer on the liner layer and contacting the liner layer.

Abstract: A semiconductor arrangement comprising a substrate having a first trench formed therein, a field plate layer arranged to extend within the first trench and coat the first trench, the field plate layer having a thickness such that it defines a second trench within the first trench, a barrier layer arranged to coat an internal surface of the second trench; and a trench fill material configured to substantially planarize the first and second trenches.