Abstract: Apparatus for controlling sensors is provided. The solution comprises an apparatus having a first interface (102) comprising device addresses for connecting sensors (104, 106), each sensor comprising an identification and registers for monitoring and controlling the sensor; a second interface (108) for communicating with external devices. The apparatus is configured to configured to control the second interface (108) to receive a message in symbol format, the message comprising a sender id, a recipient id and the register address of a sensor; to process messages received from external devices, the messages related to sensors; direct using the first interface the message to the register address if the recipient identification is the identification of sensor.

Abstract: Disclosed is a memory circuit and method of forming the same. The memory circuit comprises a lower metallization layer defining first conducting lines. A continuous magnetic storage element stack is atop the lower metallization layer wherein a bottom electrode of the stack is in direct contact with the first conducting lines. An upper metallization layer is atop the continuous magnetic storage element stack, the upper metallization layer defining second conducting lines, which are in direct contact with said continuous magnetic storage element stack. Localized areas of the continuous magnetic storage element stack define discrete magnetic bits, each energizable through a selected pair of the first and second conducting lines. In a second aspect and a third aspect, the continuous magnetic storage element stack is respectively partially and fully etched through a single mask, to define the discrete magnetic bits.

Abstract: A thin film transistor (TFT) circuit device comprises a substrate comprising a major surface; a gate line formed over the substrate and extending in a first direction when viewed in a viewing direction perpendicular to the major surface; an insulating layer formed over the gate line; an electrically conductive line formed over the insulating layer and extending in a second direction when viewed in the viewing direction, the second direction being different from the first direction, the electrically conductive line comprising a source line or a data line; and a semiconductor piece formed over the substrate. The semiconductor piece comprises a portion which is located between the substrate and the gate line and overlaps the gate line and the electrically conductive line at an intersection of the gate line and the electrically conductive line when viewed in the viewing direction.

Abstract: A semiconductor light-emitting structure and a semiconductor package structure thereof are provided. The semiconductor light-emitting structure includes a first-type semiconductor layer, an active layer, a second-type semiconductor layer, a metal layer and a distributed Bragg reflector. The active layer is disposed on the first-type semiconductor layer. The second-type semiconductor layer is disposed on the active layer. The metal layer is disposed on the second-type semiconductor layer as a first reflective structure, wherein the metal layer has an opening portion. The distributed Bragg reflector is disposed on the metal layer and interposed into the opening portion as a second reflective structure. The first reflective structure and the second reflective structure form a reflective surface on the second-type semiconductor layer.

Abstract: Stripe-shaped surface transistor structures of a power MOSFET are disposed over an array of parallel-extending P type Buried Stripe-Shaped Charge Compensation Regions (BSSCCRs). The power MOSFET has two and only two epitaxial semiconductor layers, and the BSSCCRs are disposed at the interface between these layers. Looping around the area occupied by these parallel-extending BSSCCRs is a P type ring-shaped BSSCCR. At the upper semiconductor surface are disposed three P type surface rings. The inner surface ring and outer surface ring are coupled together by a bridging metal member, but the center surface ring is floating. The bridging metal member is disposed at least in part over the ring-shaped BSSCCR. The MOSFET has a high breakdown voltage, a low RDS(ON), and is acceptable and suitable for manufacture at semiconductor fabrication plants that cannot or typically do not make superjunction MOSFETs.

Abstract: The present disclosure provides CMOS image sensors and fabrication methods thereof. An exemplary fabrication process of a CMOS image sensor includes providing a substrate having a first region and a second region connecting with the first region at a first end of the first region; forming a transfer transistor on surface of the substrate in the second region; forming a first implanting region in the substrate in the first region using a first mask; forming a second implanting region in the first implanting region by, the first implanting region being separated into a third implanting region on the second implanting region and a fourth implanting region under the second implanting region; forming a fifth region in the second region at the first end using a second mask, connecting the third implanting region with the fourth implanting region.

Abstract: A method of fabricating a semiconductor device is provided. A plurality of target patterns is formed on a substrate. The plurality of target patterns is extended in parallel to each other along a first direction. A first mask pattern extending in the first direction and including a plurality of first openings is formed. A second mask pattern extending in a second direction crossing the first direction and including a plurality of second openings is formed. Each second opening overlaps each first opening to form an overlapped opening region. A region of the plurality of target patterns is etched through the overlapped opening region using the first mask pattern and the second mask pattern as a etch mask. The region of the plurality of target patterns is overlapped with the overlapped opening region.

Abstract: An apparatus, system, and method are provided for a vertical two-terminal nanotube or microtube device configured to capture and generate energy, to store electrical energy, and to integrate these functions with power management circuitry. The vertical device can include a column disposed in a template material extending from one side of the template material to the other side of the template material. Further, the device can include a first material disposed within the column, a second material disposed within the column, and a third material disposed in the column. A variety of configurations, variations, and modifications are provided.

Abstract: An integrated circuit (IC) that includes a circuit substrate having a front side surface and an opposite back side surface. Active circuitry is located on the front side surface. An inductive structure is located within a deep trench formed in the circuit substrate below the backside surface. The inductive structure is coupled to the active circuitry.

Abstract: Human Computer Interfaces (HCI) may allow a user to interact with a computer via a variety of mechanisms, such as hand, head, and body gestures. Various of the disclosed embodiments allow information captured from a depth camera on an HCI system to be used to recognize such gestures. Particularly, the HCI system's depth sensor may capture depth frames of the user's movements over time. To discern gestures from these movements, the system may group portions of the user's anatomy represented by the depth data into classes. This grouping may require that the relevant depth data be extracted from the depth frame. Such extraction may itself require that appropriate clipping planes be determined. Various of the disclosed embodiments better establish floor planes from which such clipping planes may be derived.

Abstract: An integrated circuit containing a bipolar transistor including an emitter diffused region with a peak doping density higher than 1·1020 atoms/cm3, and an emitter-base junction less than 40 nanometers deep in a base layer. A process of forming the bipolar transistor, which includes forming an emitter dopant atom layer between a base layer and an emitter layer, followed by a flash or laser anneal step to diffuse dopant atoms from the emitter dopant atom layer into the base layer.

Abstract: A reliable semiconductor light-emitting device can include a mounting board, at least one semiconductor light-emitting chip mounted on the mounting board, a wavelength converting layer having a side surface covering the light-emitting chip, and a seal member having an opening contacting the side surface of the wavelength converting layer and covering chip electrodes. The light-emitting device can also include a transparent layer disposed into the opening of the sealing member so as to be located over the light-emitting chip and within a top surface of the light-emitting chip, and can be configured to emit various mixture lights having a high uniformity by using lights emitted from the light-emitting chip and the wavelength converting layer. Thus, the disclosed subject matter can provide the reliable light-emitting device, which can emit the mixture lights including a substantially white color light from a small light-emitting surface as a light source for a headlight, etc.

Abstract: A method of forming an electronic device includes forming a first opening and a second opening in a workpiece. The first opening is deeper than the second opening. The method further includes forming a fill material within the first opening to form part of a through via and forming the fill material within the second opening.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a dielectric layer on a substrate; forming a stop layer between the dielectric layer and the substrate, wherein the stop layer contacts the substrate directly and the dielectric layer covers the top surface of the stop layer; forming an opening in the dielectric layer, wherein the dielectric layer comprises a damaged layer adjacent to the opening; forming a dielectric protective layer in the opening; forming a metal layer in the opening; removing the damaged layer and the dielectric protective layer to form a void, wherein the void exposes a top surface of the substrate; and forming a cap layer on and covering the dielectric layer, the void, and the metal layer.

Abstract: A semiconductor package includes a semiconductor substrate and an electrode pad formed on the semiconductor substrate. The electrode pad includes a central portion and a peripheral portion, and a first pattern is located on the peripheral portion. A passivation layer is formed on the semiconductor substrate and the electrode pad. The passivation layer has an opening exposing the central portion of the electrode pad and a second pattern located on the first pattern. A seed layer is formed on the electrode pad and the passivation layer. The seed layer has a third pattern formed on the second pattern. A bump is formed on the seed layer and electrically connected to the electrode pad. An undercut is formed around the third pattern located under an edge of a lower portion of the bump.

Abstract: A method of forming a resistive memory cell, e.g., a CBRAM or ReRAM cell, may include forming a plurality of bottom electrode connections, depositing a bottom electrode layer over the bottom electrode connections, performing an etch to remove portions of the bottom electrode layer to form at least one upwardly-pointing bottom electrode region above the bottom electrode connections, each upwardly-pointing bottom electrode region defining a bottom electrode tip, and forming an electrolyte region and a top electrode over each bottom electrode tip such that the electrolyte region is arranged between the top electrode and the respective bottom electrode top.

Abstract: A bipolar transistor has a subcollector layer and a stack of collector, base, and emitter layers on the subcollector layer. On the subcollector layer are collector electrodes. On the base layer are base electrodes. The collector layer includes multiple doped layers with graded impurity concentrations, higher on the subcollector layer side and lower on the base layer side. Of these doped layers, the one having the highest impurity concentration is in contact with the subcollector layer and has a sheet resistance less than or equal to about nine times that of the subcollector layer.

Abstract: A semiconductor device includes a semiconductor substrate having a principal surface which has a first side in a first direction and a second side in a second direction. A plurality of transistor arrays is formed in a region adjacent to the first side of the semiconductor substrate. A plurality of bumps include first and second bumps which are longer in the first direction. The distance between the first side and the first bump is shorter than the distance between the first side and the second bump. The plurality of transistor arrays include a first and a second transistor arrays. The first transistor array has a plurality of first unit transistors arranged along the first direction such that the first unit transistors overlap the first bump. The second transistor array has a plurality of second unit transistors arranged along the first direction such that the second unit transistors overlap the second bump.

Abstract: A red phosphor contains a nitride having a formula of SrxMgySizN2/3(x+y+2z+w):Euw, in which x, y, z, and w satisfy the relationships 0.5?x?2, 2.5?y?3.5, 0.5?z?1.5 and 0<w?0.1. The red phosphor is configured to emit light having a peak wavelength in a range of from 610 nm to 625 nm when irradiated by an excitation source, and the excitation source may be a blue light source having a dominant wavelength in a range of 420 nm to 470 nm. In such a case, the spectrum of the emitted light has a full-width at half-maximum (FWHM) less than or equal to 55 nm.

Abstract: An image sensor pixel may include a photodiode, a floating diffusion, and a transfer gate. A buried channel may be formed under the transfer gate. The buried channel may extend from the floating diffusion to overlap a portion of the transfer gate without extending completely beneath the transfer gate or reaching the photodiode. The buried channel may provide a path for antiblooming current from the photodiode to reach the floating diffusion, while allowing for the transfer gate off voltage to remain high enough to prevent transfer gate dark current from flowing into the photodiode.