Patents Examined by Laura Thomas
  • Patent number: 5834705
    Abstract: An apparatus for modifying a printed circuit board comprised of a nonconductively adhering flexible circuitized substrate, the flexible circuitized substrate having a conductive circuit trace composed of one or more layers of thin wires sandwiched between two or more layers of flexible insulating protective material. The wires forming the circuit trace of the flexible substrate and the conductors forming the circuitry in and on the printed circuit board are electrically interconnected at appropriate predetermined positions by establishing conductive paths through portions of the insulating layers of the flexible circuitized substrate. Circuit components can also be affixed to either the flexible circuitized substrate or to the printed circuit board or to both after the flexible circuitized substrate has been affixed to the printed circuit board.
    Type: Grant
    Filed: March 4, 1994
    Date of Patent: November 10, 1998
    Assignee: Silicon Graphics, Inc.
    Inventor: Siamak Jonaidi
  • Patent number: 5790382
    Abstract: A relatively large printed circuit board includes a pair of stiffening members for preventing bending of the board during handling. The stiffening members are disposed along opposite sides of the board and include edge portions abutting against the board side surfaces and forming planar side extensions of the board. The member edge portions adjoin lateral extensions which are off-set from the plane of the edge portions and which lie flat against a substrate major surface and there secured to the substrate. A beam is rigidly secured to the lateral extension of each member by means of spaced apart posts. The beam overlies the lateral extension and functions, in combination with the lateral extension and post, as a lattice-type I-beam.
    Type: Grant
    Filed: December 26, 1995
    Date of Patent: August 4, 1998
    Assignee: Lucent Technologies Inc.
    Inventor: Eric T. Sexton
  • Patent number: 5723823
    Abstract: A rework configuration is provided for disconnecting defective lithography-formed conductors and/or overlying electrical components from the printed circuit wiring netlist and connecting rework elements at the substituted sites. In particular, defective regions can be severed at spaced first and second target areas upon the upper surface of the PCB and one or more interconnect structures can be coupled therebetween. The interconnect structures allow re-routing of PCB conductors, allow connectivity between the upper and lower surfaces, allow connectivity to power and ground planes, and allow pull-up, pull-down and decoupling connectivity.
    Type: Grant
    Filed: June 9, 1994
    Date of Patent: March 3, 1998
    Assignee: Dell USA, L.P.
    Inventor: James S. Bell
  • Patent number: 5682018
    Abstract: Structures, and methods of fabrication thereof, are described wherein between an electrically conducting region and a ceramic region there is an interface region which has a thermal coefficient of expansion which is intermediate between the thermal coefficient of expansion of the conducting region and the ceramic region. This interface region substantially avoids separation of the adhesion of the conducting region from the ceramic region and avoids the creation of voids therebetween. The interface region is preferably a mixture of metal particles and ceramic material. The interface region is created by sintering alternately in oxidizing and reducing atmospheres which results in metal particles being disposed away from the metal body about the periphery of the metal body within the ceramic material.
    Type: Grant
    Filed: October 18, 1991
    Date of Patent: October 28, 1997
    Assignee: International Business Machines Corporation
    Inventors: Sheree Hsiao-Ru Wen, Carl Stephen Wood
  • Patent number: 5682297
    Abstract: A dual footprint for servicing either of two types of microprocessor packaging systems. A first footprint capable of receiving and servicing a first type of microprocessor packaging system, for example, a tape carrier package microprocessor package, is formed within a second footprint capable of receiving and servicing a second type of microprocessor packaging system, for example, a pin grid array microprocessor package. In a preferred form, the two footprints are electrically interconnected and the first footprint is offset by a selected angle from the second footprint to allow increased connectivity between the two footprints.
    Type: Grant
    Filed: March 12, 1996
    Date of Patent: October 28, 1997
    Assignee: AST Research, Inc.
    Inventor: David J. Silva
  • Patent number: 5679928
    Abstract: A connection terminal portion of a substrate and a terminal portion of an external circuit substrate or a terminal portion of a part are electrically connected together using an anisotropic electrically conducting film. A structure in which a first substrate having a connection terminal portion and a second substrate having a connection terminal portion or a connection terminal portion of a part are connected together with an anisotropic electrically conducting adhesive containing electrically conducting particles, wherein the thickness of the electrically conducting film provided for the connection terminal of the first substrate, the second substrate or the part is smaller than the diameter of the electrically conducting particles. The invention is further concerned with a method of accomplishing the electrical connection.
    Type: Grant
    Filed: March 24, 1995
    Date of Patent: October 21, 1997
    Assignee: Citizen Watch Co., Ltd.
    Inventors: Akihiko Okano, Terutaka Okano
  • Patent number: 5679929
    Abstract: The present invention provides anti-bridging pad(s) for wave soldering of interconnecting substrates. In particular, the present invention provides interconnecting substrates (e.g. printed circuit board) having anti-bridging pad(s) which substantially conform to trailing pad(s), have geometries and/or placements with respect to trailing pad(s) in an array of functional pads which reduce or eliminate solder bridging.
    Type: Grant
    Filed: July 28, 1995
    Date of Patent: October 21, 1997
    Assignee: Solectron Corporqtion
    Inventors: Douglas Wayne Greenfield, Richard Paul Yorkovich
  • Patent number: 5677515
    Abstract: A shielded printed wiring board is disclosed which provides electrical and magnetic isolation for the signal layers located thereon. The printed wiring board includes a signal layer laminated between two non-conductive dielectric layers. The bottom side of the printed wiring board has a conductive layer coated thereon. Grooves are routed through the printed circuit board on both sides of each signal layer extending from the top layer partially through to the conductive layer. Conductive metallic coatings are then provided to coat the board and thereby encapsulate the signal layer in a ground envelope, separated by a controlled thickness dielectric. In an alternate embodiment, a plurality of layers are laminated one on top of the other to provide a multilayer printed wiring board.
    Type: Grant
    Filed: October 18, 1991
    Date of Patent: October 14, 1997
    Assignee: TRW Inc.
    Inventors: Kenneth Charles Selk, Harold J. Hirsch, James Carl Canyon, Frederick M. Gower
  • Patent number: 5674077
    Abstract: Connectors on a microcomputer printed circuit board backplane receive slotted insertion of a plurality of device cards containing application specific integrated circuits (ASICs). Interconnection of the device card connectors is accomplished on the surface of the circuit board or internally with an electric line which interleaves the device card connectors providing increased conductor length between physically adjacent connectors, establishing an increased impedance level. The increased physical lengths of the intervening electric lines between the connectors provide increased impedance as seen by inserted device cards, which enhances the matching capabilities of the connectors.
    Type: Grant
    Filed: September 30, 1994
    Date of Patent: October 7, 1997
    Assignee: Apple Computer, Inc.
    Inventors: Charles M. Flaig, William Todd Krein
  • Patent number: 5670749
    Abstract: A multilayer circuit board or laminated circuit board for use in a motor controller is described. The multilayer circuit board is preferably utilized as a power substrate module. The power substrate module includes a mounting area provided in a recess, window or portion of the circuit board where the circuit board is only a single layer thick. The insulated mounting area is provided in a blind via in the multilayer circuit board. The single circuit board layer at the mounting area provides a heat conductive yet highly electrically insulated mounting area for receiving a heat sink. The heat sink can be mounted on a side opposite the electrical device. The heat sink may be standard heat sink or a copper coil directly soldered to the circuit board. The multilayer circuit board includes an enhanced conductive layer for receiving the surface mount device. The enhanced conductive layer preferably includes an insulative frame which holds copper slugs.
    Type: Grant
    Filed: September 29, 1995
    Date of Patent: September 23, 1997
    Assignee: Allen-Bradley Company, Inc.
    Inventors: Christopher J. Wieloch, Thomas E. Babinski, John C. Mather
  • Patent number: 5670750
    Abstract: A metal carrier has a dielectric material with a thickness of less than 0.004 inch and electrical voltage insulation characteristics of at least 2500 volts formed on a surface. A donut configured land defines at least one via or opening for removing dielectric material selectively. Reflow solder is used to form electrical interconnections, and the vias provide thermal dissipation sufficient to conform to safety requirements.
    Type: Grant
    Filed: April 27, 1995
    Date of Patent: September 23, 1997
    Assignee: International Business Machines Corporation
    Inventors: John Matthew Lauffer, David John Russell, James Jens Hansen
  • Patent number: 5663529
    Abstract: A footprint, and method for forming the footprint, of the type for mounting a surface mount component having a heatsink which defines a first registration edge thereon. The substrate pad is positioned on the substrate for registrated engagement with the heatsink. The substrate pad has an area substantially larger than the area of the heatsink to improve the dissipation of thermal energy. The substrate pad includes notches for defining registration edges which are juxtaposed with corresponding registration edges on the heatsink when the electronic component is in proper alignment with the substrate pad. Surface tension forces produced by melting solder interposed between the heatsink and the substrate pad act upon the registration edges to maintain proper alignment of the component with the substrate pad.
    Type: Grant
    Filed: September 14, 1995
    Date of Patent: September 2, 1997
    Assignee: Ford Motor Company
    Inventors: Richard Keith McMillan, II, Vivek Amir Jairazbhoy
  • Patent number: 5663530
    Abstract: A tape ball grid array package reverses the usual attachment of flexible circuitry to a stiffener so that the circuit traces face the stiffener rather than away from the stiffener as is conventional. This construction allows the elimination of a previously necessary solder mask and so reduces the cost to produce the package.
    Type: Grant
    Filed: August 1, 1995
    Date of Patent: September 2, 1997
    Assignee: Minnesota Mining and Manufacturing Company
    Inventors: Randolph D. Schueller, Anthony R. Plepys, Howard E. Evans
  • Patent number: 5659153
    Abstract: The present invention provides a wiring module containing a plurality of laminated polymer layers containing defined electronic circuitry which can be thermoformed into desired three dimensional shapes without damaging the internal wiring at the region of thermoform stress. More particularly, the invention provides a thermoformed, three dimensional wiring module prepared by thermoforming a laminate comprising a plurality of laminated, thermoformable polymer insulating layers containing conductive wiring circuitry on at least one surface of the layers, the layers being assembled to form conductive interconnect paths within the module, the module further characterized in that the conductive wiring circuitry is present only on internal low stress layers of the laminate at the region of thermoformed bends present in the module.
    Type: Grant
    Filed: March 3, 1995
    Date of Patent: August 19, 1997
    Assignee: International Business Machines Corporation
    Inventors: Chandrasekhar Narayan, Jane Margaret Shaw
  • Patent number: 5656798
    Abstract: A circuit board has holes extending therethrough, and a solder layer disposed on a first side of the board. Terminals have been pushed through respective holes and into contact with the solder layer. The terminals have been welded to the first side of the circuit board in a fluxless manner by an irradiated energy beam.
    Type: Grant
    Filed: December 19, 1995
    Date of Patent: August 12, 1997
    Assignee: Matsushita Electric Works, Ltd.
    Inventors: Masao Kubo, Kazuo Kamada, Masanobu Ogasawara, Yoshimitsu Nakamura
  • Patent number: 5654528
    Abstract: A cover layer of a flexible printed circuit includes a first hole and a plurality of openings. The first hole has substantially the same diameter as that of a positioning piece of an inspection machine. A distance between the first hole and each of the openings is predetermined. After the cover layer is adhered to the base member, a second hole is formed on the base member inside the first hole. A diameter of the second hole is smaller than that of the first hole. At the time of a continuity test, the second hole is deformed by a insertion of the portioning piece, so that the positioning piece is inserted into the first hole. As a result, the flexible printed circuit is positioned on the basis of the first hole.
    Type: Grant
    Filed: November 20, 1995
    Date of Patent: August 5, 1997
    Assignee: Fuji Photo Optical Co., Ltd.
    Inventor: Kazuhisa Tanaka
  • Patent number: 5652557
    Abstract: A transmission line including a dielectric or semi-insulating substrate; a groove in the substrate; a metallization film disposed on the bottom surface of the groove; a dielectric filling the groove and making contact with the metallization film; a wiring conductor film disposed on the dielectric; and a grounding metallization film disposed on the rear surface of the substrate. Excellent confinement of electromagnetic waves is achieved and electromagnetic wave interference between two neighboring lines is extremely small, realizing a high density arrangement of transmission lines and a compact and lightweight microwave/millimeter wave integrated circuit. Higher modes of electromagnetic wave propagation are avoided by controlling the thickness of the dielectric filling the groove while the thickness of the substrate remains arbitrary, thereby improving production yield and reliability.
    Type: Grant
    Filed: October 17, 1995
    Date of Patent: July 29, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Takahide Ishikawa
  • Patent number: 5650595
    Abstract: The present method employs a first plating resist for forming circuit lines on a carrier substrate. While the plating resist is still in place a metal, such as nickel, is deposited on top of the circuit lines. A second plating resist is employed for plating solder on the circuit lines at solder sites. At this stage additional solder can be deposited at each solder site to provide or supplement the necessary low melt solder required for forming a solder joint. The first and second resists along with solder thereon are then stripped and copper foil on the carrier substrate is etched away around the circuit lines. A soldermask is then formed on the carrier substrate over the circuit lines except for circuit lines in the chip sites. The soldermask has a single large opening at each chip site which has lateral dimensions which are slightly larger than the lateral dimensions of the chip to be connected at the chip site.
    Type: Grant
    Filed: May 25, 1995
    Date of Patent: July 22, 1997
    Assignee: International Business Machines Corporation
    Inventors: Mark Rudolf Bentlage, Kenneth Michael Fallon, Lawrence Harold White
  • Patent number: 5646368
    Abstract: A multi-layered printed circuit board having an integrated twisted pair conductor. In a preferred embodiment, the printed circuit board comprises two segmented conductor traces on a first and a second layer of the printed circuit board crisscrossing each other and a plurality of vias. The two segmented conductor traces on the first layer are connected to the two segmented conductor traces on the second layer through the vias. The twisted pair conductor may be shielded by adding a ground trace on either side of the conductor traces and a ground plane both above and below the conductor traces. The conductor traces may also be tuned to specific electrical characteristics by properly spacing the plurality of vias such that a specific number of turns per unit length are achieved. The continuous conductor traces may be further tuned by using a specific dielectric thickness as well as by designing the conductor traces to be of a specific dimension.
    Type: Grant
    Filed: November 30, 1995
    Date of Patent: July 8, 1997
    Assignee: International Business Machines Corporation
    Inventors: Jorge Enrique Muyshondt, Gary Parker, Bruce James Wilkie
  • Patent number: 5644475
    Abstract: A solder resist pattern for a single in-line package (SIP) finger connector, or other interface member includes small solder resist features spaced closely together. The features can be circular, square, diamond-shaped, star-shaped, or other geometry and preferably are placed on finger connectors in a photo-imaging process. The pattern includes meniscus channels which are narrow enough to prevent solder from adhering to the finger connectors. The surface area of the features is small enough so that the pattern can be easily removed by a low impact or non-contact operation. Preferably, the pattern is removed by a hot air solder knife after the board is subjected to a solder wave.
    Type: Grant
    Filed: April 11, 1995
    Date of Patent: July 1, 1997
    Assignee: Allen-Bradley Company, Inc.
    Inventors: Gerard A. Woychik, John C. Mather