Patents Examined by Laura Thomas
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Patent number: 5623127Abstract: A solder clad printed circuit board (100) consists of an electrically insulating substrate that has copper circuit traces (105), portions of which are solderable. A substantially planar layer (120) of a soldering composition is fused to the solderable traces, to form a solder pad that is not domed. The layer is composed of a mass of off-eutectic solder particles (115) that are fused together to form an agglomeration (120) having a porous structure. The solder particles are fused together by heating the off-eutectic solder to a temperature that is between the solidus temperature and the liquidus temperature of the solder. The solder is then cooled below the solidus temperature to solidify it.Type: GrantFiled: December 2, 1994Date of Patent: April 22, 1997Assignee: Motorola, Inc.Inventors: Edwin L. Bradley, III, Kingshuk Banerji, William B. Mullen, III
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Patent number: 5621372Abstract: A single phase, dry type transformer has an iron core, high voltage windings embedded in cast resin, and low voltage windings resin encapsulated. The low voltage winding is constructed with flexible sheet conductors. Insulating material includes a means to secure the windings in place during a vacuum and pressure resin impregnation process. The result is a coil that exhibits high short circuit protection due to the tightly bond conductors comparable to completely resin encased molded transformers at a substantially reduced cost.Type: GrantFiled: September 20, 1994Date of Patent: April 15, 1997Assignee: Square D CompanyInventor: Dilip R. Purohit
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Patent number: 5621193Abstract: A method for electrically connecting a surface conductor to an edge conductor on an intersecting side of a non-conductive substrate, includes the steps of forming a through-hole in the substrate, and metallizing the through-hole to form a conductive via. Then, the substrate through the via is cut to form an intersecting side. An electrical connection may be made between a surface conductor through the via to an edge conductor on the intersecting side of the substrate. A preferred embodiment further includes forming an insulating sealing plug in the via, prior to cutting the intersecting side. The above method provides an edge connection without the need to wrap a conductive conduit around the corner of the substrate. Such wrap-around conduits are vulnerable to damage during subsequent handling of the substrate.Type: GrantFiled: May 23, 1995Date of Patent: April 15, 1997Assignee: Northrop Grumman CorporationInventor: Harlan R. Isaak
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Patent number: 5619013Abstract: A gangable electrical box includes a main body and a pair of removable sidewalls. The main body has opposite side edges, each side edges having a pair of flanges extending from a midpoint on a rear panel and along the end panels. The sidewalls include flanges along each transverse edge and a pair of flanges on the longitudinal edge. The flanges on the sidewall are formed to complement the flanges on the main body to overlap with each other in a coupling relation. The main body and sidewalls are formed from a folded blank. The flanges of the main body are arranged so that a plurality of identical main bodies can be ganged with the flanges of a first main body telescoping with the flanges of a second main body.Type: GrantFiled: December 17, 1993Date of Patent: April 8, 1997Assignee: Hubbell IncorporatedInventor: Robert W. Jorgensen
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Patent number: 5619018Abstract: A multilayer printed circuit board comprising conducting layers of a first material and conducting layers of a second material includes noncorrosive low resistance electrical contacts between conducting layers of the first and second material. The noncorrosive low resistance contacts allow the use of light weight conducting materials for particular layers of the circuit board to produce a light weight multilayer circuit board.Type: GrantFiled: April 3, 1995Date of Patent: April 8, 1997Assignee: Compaq Computer CorporationInventor: Markku J. Rossi
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Patent number: 5619017Abstract: A method of connecting a semiconductor chip assembly having at least first and second contacts to a connection component including at least first and second connection leads by means of a tool consisting of the steps of juxtaposing moving and connecting the leads to the corresponding contacts. The connection component is juxtaposed with the semiconductor chip assembly so that the first and second connection leads are aligned with the first and second contacts in such a manner that the first connection lead is offset from the first contact in the first direction and the second connection lead is offset from the second contact in the same first direction.Type: GrantFiled: November 1, 1995Date of Patent: April 8, 1997Assignee: Tessera, Inc.Inventors: Thomas H. Distefano, Zlata Kovac, John Grange
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Patent number: 5616888Abstract: A rigid-flex multilayer circuit board or laminated circuit board includes an insulated mounting area for a surface mount package. The mounting area is provided in a recess or portion of the circuit board where the circuit board is only a single flexible circuit board layer thick. The insulated mounting area is provided in a blind via in the multilayer circuit board. The insulating medium associated with the single flexible circuit board layer is less than 2.0 mils thick and includes polyimide. The single flexible circuit board layer provides a heat conductive yet highly electrically insulative mounting area for receiving a heat sink. The heat sink can be mounted on a side opposite the electrical device. The heat sink may be a standard heat sink or a copper coil directly soldered to the circuit board. The heat sink mounting area eliminates the need for bolts, nuts, brackets, and an additional insulating layer necessary to insulate power semiconductor components.Type: GrantFiled: September 29, 1995Date of Patent: April 1, 1997Assignee: Allen-Bradley Company, Inc.Inventors: Steven R. McLaughlin, Christopher J. Wieloch, John C. Mather
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Patent number: 5614698Abstract: The substrate member of a multi-tier circuit board is provided, during the construction thereof, with an integral bar code structure by extending spaced apart, parallel finger sections of an interior metal ground plane portion of a panel structure outwardly past the routing path along which the substrate member is to be separated from the panel structure. After the substrate member is routed from the panel structure it has a peripheral side edge portion upon which exposed end surface portions of the spaced ground plane finger sections are disposed in a mutually spaced bar code array representative of predetermined information relating to the completed circuit board. The ground-seeking probe portion of a conductive scanning device is moved along the bar-coded edge of the substrate member to read and decipher the integral ground plane bar code structure compactly incorporated thereon during the manufacture of the substrate member.Type: GrantFiled: January 17, 1995Date of Patent: March 25, 1997Assignee: Dell USA, L.P.Inventor: H. Scott Estes
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Patent number: 5612513Abstract: An enclosed electrical circuit and method for manufacturing the electrical circuit are provided. Initially a flexible substrate is formed with a plurality of electrical circuits. By way of example, each circuit can contain a conductive trace, a battery and a die, all in electrical communication. During the manufacturing process, a barrier is placed on the substrate and a curable encapsulant is poured into a cavity formed by the barrier and the substrate to encapsulate each circuit. The barrier can be formed as a compartmentalized dam having a separate cavity for each circuit, as a perimeter dam having a single cavity, or as a spacer sheet having a separate cavity for each circuit formed by a pattern of cut outs. Following the encapsulation step, the electrical circuits can be singulated into separate encapsulated circuits.Type: GrantFiled: September 19, 1995Date of Patent: March 18, 1997Assignee: Micron Communications, Inc.Inventors: Mark E. Tuttle, Rickie C. Lake, Joe P. Mousseau, Clay L. Cirino
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Patent number: 5612514Abstract: An apparatus for testing and connecting integrated circuit chips to external packaging and circuitry. A plurality of electrically conductive leads are formed on an electrically insulative substrate by tape automated bonding methods. The leads extend from peripherally disposed test terminals to centrally disposed interconnect pads and are aligned therebetween with bond pads that are disposed near a perimeter of a face of a chip. The leads are connected to the bond pads and are encapsulated with a cement, and the substrate is adhered to the chip face. Electronic characteristics of the chip are tested by channeling electrical signals via the test terminals. The leads are then severed closely peripheral to the bond pads, disconnecting the test terminals from the chip. The chips that pass the testing are connected via the interconnect pads, which may be arranged in a pad grid array, to matching terminals in a package.Type: GrantFiled: August 12, 1994Date of Patent: March 18, 1997Assignee: Atmel CorporationInventor: Ken Lam
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Patent number: 5612511Abstract: A double-sided electrical interconnect flexible circuit particularly useful for ink-jet pens and a method for assembling an ink-jet pen with the flexible circuit is described. A wide web, dielectric, flexible tape, such as of a polyimide material, is used to allow the substantially simultaneous formation of redundant flexible circuits across the web. The web is laminated with a conductive material foil and a plurality of redundant circuit patterns formed on the web in a single masking and etching process, or the like. A cover layer, also of a wide web format, dielectric material is coated over the circuit patterned conductive layer. Vias are provided in both the tape under layer and the tape over layer for appropriate electrical connections whereby a first device, such as an ink-jet printer controller, can be connected through one layer and a second device, such as a replaceable ink-jet pen's electrically active components can be connected through the other layer.Type: GrantFiled: September 25, 1995Date of Patent: March 18, 1997Assignee: Hewlett-Packard CompanyInventors: Neal Meyer, Byron K. Davis
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Patent number: 5612512Abstract: A high-frequency electronic component includes: a base substrate and a high-frequency electronic component element which is mounted on one face of the base substrate by soldering. The base substrate is made of bismaleimide-triazine resin.Type: GrantFiled: November 10, 1993Date of Patent: March 18, 1997Assignee: Murata Manufacturing Co., Ltd.Inventors: Hiroki Wakamatsu, Hajime Suemasa
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Patent number: 5610371Abstract: An electrical connecting device including a first circuit board providing thereon with input/output terminals, each of the terminals having a tip surface coated with gallium and a second circuit board providing thereon with contact terminals, each of the terminals having a tip surface coated with indium or tin. A low-melting point alloy layer is formed by a mutual action between gallium and indium or tin, when the input/output terminals of the first circuit board are in contact with the respective terminals of the second circuit board and the terminals are electrically connected to each other. The second metal layer includes a plurality of wire-like metal supports extending substantially perpendicular to the surface of the terminal and a low-melting point metal retained by the wire-like metal supports.Type: GrantFiled: March 14, 1995Date of Patent: March 11, 1997Assignee: Fujitsu LimitedInventors: Kaoru Hashimoto, Tatuo Chiyonobu, Kyoichiro Kawano, Koji Watanabe, Masato Wakamura, Joe Yamaguchi
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Patent number: 5608192Abstract: A multilayer thin-film wiring board formed by laminating at least three wiring layers including first, second, and third wiring layers together with a dielectric layer. The first wiring layer includes a first pattern having a plurality of first windows arranged with the same pitch both in a lateral direction and in a longitudinal direction of the wiring board, and a plurality of first island patterns each located at a substantially central portion of each first window. Similarly, the second wiring layer includes a second pattern having a plurality of second windows, and a plurality of second island patterns each located at a substantially central portion of each second window. The second windows are shifted from the first windows by half the pitch both in the lateral direction and in the longitudinal direction. The third wiring layer includes first and second via pads formed on a surface of the wiring board.Type: GrantFiled: July 26, 1995Date of Patent: March 4, 1997Assignee: Fujitsu LimitedInventors: Kiyokazu Moriizumi, Kiyotaka Seyama
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Patent number: 5608189Abstract: A screwable cable seal introduction device for employment at sleeves or housings having an introduction sheath onto which a union nut can be screwed. A press sleeve is located in the inside of the introduction sheath, an annular seal composed of sealing material and laterally arranged support rings being deformed with the press sleeve until the required adhesion of the sealing material at the sealing surfaces to be contacted is accomplished. An automatic pressure compensation subsequently occurs, so that no permanent pressure is exerted onto the introduced cable.Type: GrantFiled: June 7, 1994Date of Patent: March 4, 1997Assignee: RXS Schrumpftechnik-Garnituren GmbHInventors: Hans Winterhoff, Andreas Guenther
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Patent number: 5604333Abstract: The formation of solder bridges between pads on circuit boards is minimized by a process and structure for wicking excess solder deposited during a wave soldering process. Solder thieves are placed adjacent to a last pad of a series of pads and are approximately the same width and twice the length as the pad in order to provide sufficient wicking of solder. Thus, the excess solder is formed on the solder thieves and solder bridges are prevented.Type: GrantFiled: November 30, 1994Date of Patent: February 18, 1997Assignee: Intel CorporationInventors: Richard A. Kennish, Leslie S. Polaski
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Patent number: 5600100Abstract: An electrical device with a punched plate embedded in a plastic plate is described. The punched-out conductive contact elements are still interconnected prior to the embedding operation for ease of manipulation of the plate. The link of the conductive contact elements is a U-shaped tab which, prior to the embedding operation, stands roughly perpendicular on the conductive contact elements and is cut after the manufacture of the plastic plate. This cutting operation of the conductive contact elements is possible without holes in the plastic plate.Type: GrantFiled: August 15, 1994Date of Patent: February 4, 1997Assignee: ITT Automotive Europe GmbHInventors: Marcel Andrei-Alexandru, Peter Fein, John M. Longney
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Patent number: 5600103Abstract: A supporting member or first synthetic resin sheet with conductive bumps disposed at predetermined positions are superposed on a second synthetic resin sheet under the condition that the resin component of the second synthetic resin sheet is plastic deformed or the temperature thereof exceeds a glass transition temperature so that the conductive bumps are pierced into the second synthetic resin sheet. In other words, the conductive bumps are pierced vertically into the second synthetic resin sheet so as to form through-type conducive lead portions exposed to the first (supporting substrate) and second synthetic resin sheets. The through-type conductive lead portions are used to electrically connect electric devices and circuit and to connect wiring pattern layers. The conductive bumps can be precisely and densely formed and disposed by printing method or plating method. The conductive bumps can be pushed and pierced into the second synthetic resin sheet.Type: GrantFiled: March 2, 1994Date of Patent: February 4, 1997Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Odaira, Eiji Imamura, Yusuke Wada, Yasushi Arai, Kenji Sasaoka, Takahiro Mori, Fumitoshi Ikegaya, Sadao Kowatari
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Patent number: 5600095Abstract: A conductor splice and splice support structure and method of assembly for use with cable-in-conduit superconductor cable of the type having a plurality of spaced sub-cables each including stabilizer and superconductor strands in an annular tube. Two transition ramp members, each having a cross section varying from a first end conforming to the cable configuration to a second end having an enlarged, oval, configuration have a plurality of surface grooves each sized to hold one sub-cable. Between the two transition ramp members is provided a main support member having grooves aligned with the transition members grooves. The main support member grooves are sized to hold two overlapping sub-cables. Preferably, a braid of superconductor material is placed around the overlapping sub-cable ends. The space within the grooves surrounding the sub-cables is preferably filled with solder.Type: GrantFiled: July 18, 1994Date of Patent: February 4, 1997Assignee: Lockhead Martin CorporationInventors: Michael W. Dew, Dennis W. Lieurance, Donald C. Rix
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Patent number: 5600099Abstract: An electrical device is provided having a conductive coating or layer chemically grafted to a support substrate to produce a durable, conductive surface permanently attached to the underlying substrate material. The grafted layer can be embodied in an electrical contact, and can also be embodied as electrical traces and contact areas of circuit boards and electrical and electronic devices and components. In another embodiment, the grafted layer can be provided in an RFI/EMI shield or ground plane.Type: GrantFiled: December 2, 1994Date of Patent: February 4, 1997Assignee: Augat Inc.Inventors: David R. Crotzer, Mark G. Hanrahan, Charles S. Pickles