Patents Examined by Lauren R Bell
  • Patent number: 10818581
    Abstract: An improvement is achieved in the performance of a semiconductor device. A second component mounting portion over which a first electronic component is mounted is connected to a coupling portion of a lead frame via a suspension lead. The suspension lead has a first portion between the second component mounting portion and the coupling portion and a second portion between the first portion and the coupling portion. The second portion has a third portion connected to the first portion and having a width smaller than a width of the first portion, a fourth portion connected to the first portion and having a width smaller than the width of the first portion, and a through hole (opening) located between the third and fourth portions. Each of the first, third, and fourth portions has the same thickness. After a sealing body is formed, a cutting jig is pressed against the suspension lead to cut the suspension lead.
    Type: Grant
    Filed: July 22, 2017
    Date of Patent: October 27, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiyuki Hata, Yuichi Yato
  • Patent number: 10741767
    Abstract: In accordance with various embodiments of the disclosed subject matter, an organic thin film transistor, and a fabricating method thereof are provided. In some embodiments, the method for forming an organic thin film transistor (OTFT), comprising: forming a transparent gate layer on a transparent base substrate; forming a first initial silicone polymer layer on the transparent gate layer; and performing an oxidization process to partially oxidize the first initial silicone polymer layer to form a gate insulating layer, including an oxidized inorganic sub-layer that contacts the transparent gate layer, and a non-oxidized organic sub-layer.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: August 11, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD
    Inventor: Leilei Cheng
  • Patent number: 10589992
    Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both tungsten material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: March 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael T. Brigham, Christopher V. Jahnes, Cameron E. Luce, Jeffrey C. Maling, William J. Murphy, Anthony K. Stamper, Eric J. White
  • Patent number: 10589991
    Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both tungsten material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: March 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael T. Brigham, Christopher V. Jahnes, Cameron E. Luce, Jeffrey C. Maling, William J. Murphy, Anthony K. Stamper, Eric J. White
  • Patent number: 10553525
    Abstract: A semiconductor device has a semiconductor chip, a signal lead that is arranged in a periphery of the semiconductor chip and has a main surface and a rear surface opposed to the main surface, a wire that electrically connects the semiconductor chip and the main surface of the signal lead, and a sealing body made of sealing resin that seals the semiconductor chip, the signal lead and the wire. The signal lead has, in an extending direction of the signal lead, one end located inside the sealing body, the other end located outside the sealing body, and a wire connection region which is the main surface of the signal lead and to which the wire is connected, and an inner groove is provided in the main surface of the signal lead between the one end and the wire connection region.
    Type: Grant
    Filed: June 27, 2015
    Date of Patent: February 4, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tomoya Kashiwazaki
  • Patent number: 10549987
    Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both metal material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: February 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael T. Brigham, Christopher V. Jahnes, Cameron E. Luce, Jeffrey C. Maling, William J. Murphy, Anthony K. Stamper, Eric J. White
  • Patent number: 10553769
    Abstract: A light transmissive first insulating film having light transmissive property to visible light, a second insulating film arranged opposite to the first insulating film, a plurality of conductor patterns formed of, for example, mesh patterns having the light transmissive property to the visible light and formed on a surface of at least one of the first insulating film and the second insulating film, a plurality of first light-emitting devices connected to any two conductor patterns of the plurality of conductor patterns, and a resin layer arranged between the first insulating film and the second insulating film to hold the first light-emitting devices are included.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: February 4, 2020
    Assignee: Toshiba Hokuto Electronics Corporation
    Inventor: Keiichi Maki
  • Patent number: 10535801
    Abstract: A method of growing an AlGaN semiconductor material utilizes an excess of Ga above the stoichiometric amount typically used. The excess Ga results in the formation of band structure potential fluctuations that improve the efficiency of radiative recombination and increase light generation of optoelectronic devices, in particular ultraviolet light emitting diodes, made using the method. Several improvements in UV LED design and performance are also provided for use together with the excess Ga growth method. Devices made with the method can be used for water purification, surface sterilization, communications, and data storage and retrieval.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: January 14, 2020
    Assignee: Trustees of Boston University
    Inventors: Yitao Liao, Theodore D. Moustakas
  • Patent number: 10529844
    Abstract: A structure of trench VDMOS transistor comprises an n? epi-layer/ n+ substrate having trench gates formed therein, which have a trench oxide layer conformally formed and filled with a first poly-Si layer. A plurality of MOS structure formed on the mesas. Doubled diffused source regions are formed asides the MOS structure. An inter-metal dielectric layer is formed on the resulted surfaces. An interconnecting metal layer patterned as two is formed on inter-metal dielectric layer. The one is for source regions and the first poly-Si layer connection by source contact plugs and the other for the gate connection by gate contact plugs. In the other embodiment, the trenches are filled with a stack layer of a first oxide layer/a first poly-Si layer. The MOS gates with their second poly-Si layer in a form of rows are formed on the first oxide layer and the mesas. An inter-metal dielectric layer is formed on the resulted surfaces.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: January 7, 2020
    Assignee: CHIP INTEGRATION TECH. CO., LTD.
    Inventor: Qinhai Jin
  • Patent number: 10490553
    Abstract: Disclosed is a semiconductor device capable of functioning as a memory device. The memory device comprises a plurality of memory cells, and each of the memory cells contains a first transistor and a second transistor. The first transistor is provided over a substrate containing a semiconductor material and has a channel formation region in the substrate. The second transistor has an oxide semiconductor layer. The gate electrode of the first transistor and one of the source and drain electrodes of the second transistor are electrically connected to each other. The extremely low off current of the second transistor allows the data stored in the memory cell to be retained for a significantly long time even in the absence of supply of electric power.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: November 26, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10461220
    Abstract: A method of manufacturing a semiconductor device and the device resulted thereof is disclosed. In one aspect, the device has a heterogeneous layer stack of one or more III-V type materials, at least one transmission layer of the layer stack having a roughened or textured surface for enhancement of light transmission. The method includes (a) growing the transmission layer of a III-V type material, (b) providing a mask layer on the transmission layer, the mask layer leaving first portions of the transmission layer exposed, and (c) partially decomposing the first exposed portions of the transmission layer. Suitably redeposition occurs in a single step with decomposition, so as to obtain a textured surface based on crystal facets of a plurality of grown crystals. The resulting device has a light-emitting element. The transmission layer hereof is suitably present at the top side.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: October 29, 2019
    Assignee: IMEC
    Inventor: Kai Cheng
  • Patent number: 10373976
    Abstract: A semiconductor device includes: a substrate; an insulator layer provided on the substrate; a first transistor provided on the insulator layer; a semiconductor layer including a plurality of impurity regions of a first conduction type, the impurity regions forming a part of the first transistor; a heat dissipation layer; a thermal conductive layer linking the semiconductor layer and the heat dissipation layer; and an interruption structure configured to interrupt a flow of a current between the first transistor and the thermal conductive layer.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: August 6, 2019
    Assignee: SONY CORPORATION
    Inventors: Yuzo Fukuzaki, Hiroaki Ammo
  • Patent number: 10361392
    Abstract: A sealed structure which has high sealing capability and whose border can be slim is provided. The sealed structure includes a pair of substrates whose respective surfaces face each other with a space therebetween, and a glass layer which is in contact with the substrates, defines a space between the substrates, and has at least one corner portion and side portions in continuity with the corner portion. The width of the corner portion of the glass layer is smaller than or equal to that of the side portion of the same. The sealed structure may comprise a highly reliable light-emitting element including a layer containing a light-emitting organic compound provided between a pair of electrodes.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: July 23, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Daiki Nakamura, Yusuke Nishido
  • Patent number: 10333066
    Abstract: A pixel circuit, driving method thereof, organic light-emitting display panel and display apparatus, comprise driving transistor, first storage capacitor, collecting unit, writing unit and light-emitting unit; the collecting unit is used for collecting the threshold voltage of the driving transistor and storing the threshold voltage into the first storage capacitor, under the control of the first scan signal; the writing unit is used for storing the data voltage inputted from the input terminal for the data voltage under the control of the second scan signal; and the light-emitting unit is used for emitting lights, driven by the data voltage and a voltage inputted from the input terminal for the controllable low voltage, under the control of the light-emitting control signal. Thus, the organic light-emitting device is not affected by the threshold voltage shift of the driving transistor, which may enhance the image uniformity of the organic light-emitting display panel effectively.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: June 25, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Wenjun Hou, Ze Liu
  • Patent number: 10312290
    Abstract: Various embodiments may relate to an optoelectronic component, including an optoelectronic structure formed for providing an electromagnetic radiation, a measuring structure formed for measuring the electromagnetic radiation, and a waveguide formed for guiding the electromagnetic radiation. The optoelectronic structure and the measuring structure are optically coupled to the waveguide. The waveguide includes scattering centers distributed in a matrix, wherein the scattering centers are distributed in the matrix in such a way that part of the electromagnetic radiation is guided from the optoelectronic structure to the measuring structure.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: June 4, 2019
    Assignee: OSRAM OLED GMBH
    Inventor: Thomas Wehlus
  • Patent number: 10312246
    Abstract: A non-volatile memory cell includes a semiconductor substrate of first conductivity type, first and second spaced-apart regions in the substrate of second conductivity type, with a channel region in the substrate therebetween. A floating gate has a first portion disposed vertically over a first portion of the channel region, and a second portion disposed vertically over the first region. The floating gate includes a sloping upper surface that terminates with one or more sharp edges. An erase gate is disposed vertically over the floating gate with the one or more sharp edges facing the erase gate. A control gate has a first portion disposed laterally adjacent to the floating gate, and vertically over the first region. A select gate has a first portion disposed vertically over a second portion of the channel region, and laterally adjacent to the floating gate.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: June 4, 2019
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Jeng-Wei Yang, Man-Tang Wu, Chun-Ming Chen, Chien-Sheng Su, Nhan Do
  • Patent number: 10297607
    Abstract: A non-volatile memory having discrete isolation structures and SONOS (Silicon Oxide Nitride Oxide Silicon) memory cells, a method of operating the same, and a method of manufacturing the same are introduced. Every isolation structure on a semiconductor substrate having an array region has a plurality of gaps so as to form discrete isolation structures and thereby implant source lines in the gaps of the semiconductor substrate. Since the source lines are not severed by the isolation structures, the required quantity of barrier pins not connected to the source line is greatly reduced, thereby reducing the space required for the barrier pins in the non-volatile memory.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: May 21, 2019
    Assignee: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
    Inventors: Takao Akaogi, Yider Wu, Yi-Hsiu Chen
  • Patent number: 10283670
    Abstract: A soluble member is provided on a light emitting surface of a light emitting element. The soluble member is soluble in a solvent. The soluble member has a first surface facing the light emitting surface, a second surface opposite to the first surface in the light emitting direction, and a soluble member outer peripheral side surface provided between the first surface and the second surface. A light-blocking member made of a material which is not soluble in the solvent is provided to cover a light emitting element outer peripheral side surface and the soluble member outer peripheral side surface so that an inner side wall of the light-blocking member contacts the soluble member outer peripheral side surface. The soluble member is removed using the solvent to provide a recess surrounded by the inner side wall of the light-blocking member. A first light-transmissive member is provided in the recess.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: May 7, 2019
    Assignee: NICHIA CORPORATION
    Inventors: Toru Hashimoto, Yukihiro Shibano
  • Patent number: 10283489
    Abstract: A light emitting device, includes: three light emitting elements with different emission colors; and a package including a plurality of lead frames to individually drive the three light emitting elements, and a resin molding formed integrally with the plurality of lead frames and including an opening in a surface of the resin molding to house the light emitting elements, a portion of each of the plurality of lead frames being exposed on a bottom surface of the opening, and another portion of each of the plurality of lead frames being exposed on an outer surface of the resin molding, the three light emitting elements being disposed on one of the lead frames exposed on the bottom surface of the opening and arranged so as to form an isosceles triangle with a bottom angle of 30 to 60 degrees, and a distance between two of the light emitting elements located on a base of the isosceles triangle is one to two times a length of a side of the light emitting element located at an apex of the isosceles triangle.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: May 7, 2019
    Assignee: NICHIA CORPORATION
    Inventors: Yasuhiko Takagi, Tetsuya Yagi
  • Patent number: 10283616
    Abstract: A fabricating method of a semiconductor structure includes the following steps. A gate material layer is formed on a semiconductor substrate. A patterned mask layer is formed on the gate material layer. The pattern mask layer includes at least one opening exposing a part of the gate material layer. An impurity treatment is performed to the gate material layer partially covered by the pattern mask layer for forming at least one doped region in the gate material layer. An etching process is performed to remove the gate material layer including the doped region. A dummy gate may be formed by patterning the gate material layer, and the impurity treatment may be performed after the step of forming the dummy gate. The performance of the etching processes for removing the gate material layer and/or the dummy gate may be enhanced, and the gate material residue issue may be solved accordingly.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: May 7, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Chien Hsieh, En-Chiuan Liou, Chih-Wei Yang, Yu-Cheng Tung, Po-Wen Su