Patents Examined by Lauren R Bell
  • Patent number: 10283616
    Abstract: A fabricating method of a semiconductor structure includes the following steps. A gate material layer is formed on a semiconductor substrate. A patterned mask layer is formed on the gate material layer. The pattern mask layer includes at least one opening exposing a part of the gate material layer. An impurity treatment is performed to the gate material layer partially covered by the pattern mask layer for forming at least one doped region in the gate material layer. An etching process is performed to remove the gate material layer including the doped region. A dummy gate may be formed by patterning the gate material layer, and the impurity treatment may be performed after the step of forming the dummy gate. The performance of the etching processes for removing the gate material layer and/or the dummy gate may be enhanced, and the gate material residue issue may be solved accordingly.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: May 7, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Chien Hsieh, En-Chiuan Liou, Chih-Wei Yang, Yu-Cheng Tung, Po-Wen Su
  • Patent number: 10211289
    Abstract: A semiconductor device may include a semiconductor substrate. The semiconductor device may further include a gate electrode that overlaps the semiconductor substrate. The semiconductor device may further include a channel region that overlaps at least one of the gate electrode and the semiconductor substrate. The semiconductor device may further include a stress adjustment element that contacts the channel region and is positioned between the channel region and a surface of the semiconductor substrate in a direction perpendicular to the surface of the semiconductor substrate. A maximum width of the channel region in a direction parallel to the surface of the semiconductor substrate is greater than a maximum width of the stress adjustment element in the direction parallel to the surface of the semiconductor substrate in a cross-sectional view of the semiconductor device.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: February 19, 2019
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Meng Zhao
  • Patent number: 10163891
    Abstract: A device comprises a high voltage n well and a high voltage p well over a buried layer, a first low voltage n well over the high voltage n well, wherein a bottom portion of the first low voltage n well is surrounded by the high voltage n well, an N+ region over the first low voltage n well, a second low voltage n well and a low voltage p well over the high voltage p well, a first P+ region over the second low voltage n well and a second P+ region over the low voltage p well.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Feng Chang, Jam-Wem Lee
  • Patent number: 10153290
    Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a substrate; a field effect transistor disposed in a periphery region of the substrate, the field effect transistor including a gate electrode, a first source, a first drain; a floating gate non-volatile memory device disposed in a memory region of the substrate, the floating gate non-volatile memory device including a second source, a third source, and a second drain, wherein the second source, the third source, and the second drain are disposed along an axis; and a floating gate electrode in the memory region including a first portion, a second portion, and a third portion, wherein the first portion, the second portion, and the third portion are electrically connected, wherein the first portion, the second portion and the third portion extend perpendicular to the axis.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: December 11, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Felix Ying-Kit Tsui, Huang-Wen Tseng
  • Patent number: 10128270
    Abstract: The present disclosure relates to a method for manufacturing an active matrix substrate. A first laminated film in which a semiconductor film, a first transparent conductive film, and a first metal film are laminated is formed on a substrate. A photoresist pattern having a first part covering a formation area of a channel part of a thin film transistor, a second part covering a formation area of a pixel electrode, and a third part covering formation areas of a source electrode, a drain electrode, and a source line, is formed on the first laminated film. The first metal film, the first transparent conductive film, and the semiconductor film are patterned using the photoresist pattern; the first part is removed and the first metal film and the first transparent conductive film are patterned; and the second part is removed and the first metal film is patterned.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: November 13, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Nobuaki Ishiga, Kazunori Inoue, Naoki Tsumura, Kensuke Nagayama, Yasuyoshi Ito
  • Patent number: 10053361
    Abstract: A microelectromechanical systems (MEMS) package includes a eutectic bonding structure free of a native oxide layer and an anti-stiction layer, while also including a MEMS device having a top surface and sidewalls lined with the anti-stiction layer. The MEMS device is arranged within a MEMS substrate having a first eutectic bonding substructure arranged thereon. A cap substrate having a second eutectic bonding substructure arranged thereon is eutectically bonded to the MEMS substrate with a eutectic bond at the interface of the first and second eutectic bonding substructures. The anti-stiction layer lines a top surface and sidewalls of the MEMS device, but not the first and second eutectic bonding substructures. A method for manufacturing the MEMS package and a process system for selective plasma treatment are also provided.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: August 21, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yuan-Chih Hsieh, Hung-Hua Lin, Wen-Chuan Tai, Hsiang-Fu Chen
  • Patent number: 9954004
    Abstract: The degree of integration of a semiconductor device is enhanced and the storage capacity per unit area is increased. The semiconductor device includes a first transistor provided in a semiconductor substrate and a second transistor provided over the first transistor. In addition, an upper portion of a semiconductor layer of the second transistor is in contact with a wiring, and a lower portion thereof is in contact with a gate electrode of the first transistor. With such a structure, the wiring and the gate electrode of the first transistor can serve as a source electrode and a drain electrode of the second transistor, respectively. Accordingly, the area occupied by the semiconductor device can be reduced.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: April 24, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9954050
    Abstract: A resistive material is formed straddling over each semiconductor fin that extends upward from a surface of a substrate. The resistive material is then disconnected by removing the resistive material from atop each semiconductor fin. Remaining resistive material in the form of a U-shaped resistive material liner is present between each semiconductor fin. Contact structures are formed perpendicular to each semiconductor fin and contacting a portion of a first set of the semiconductor fins and a first set of the U-shaped resistive material liners.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: April 24, 2018
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Shanti Pancharatnam, Alexander Reznicek, Oscar van der Straten
  • Patent number: 9941363
    Abstract: A semiconductor device comprises a first layer of a substrate arranged on a second layer of the substrate the second layer of the substrate including a doped III-V semiconductor material barrier layer, a gate stack arranged on a channel region of the first layer of a substrate, a spacer arranged adjacent to the gate stack on the first layer of the substrate, an undoped epitaxially grown III-V semiconductor material region arranged on the second layer of the substrate, and an epitaxially grown source/drain region arranged on the undoped epitaxially grown III-V semiconductor material region, and a portion of the first layer of the substrate.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: April 10, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng-Wei Cheng, Pranita Kerber, Amlan Majumdar, Yanning Sun
  • Patent number: 9922936
    Abstract: A type III-V semiconductor substrate is provided. Semiconductor material is removed from the type III-V semiconductor substrate such that the type III-V semiconductor substrate comprises one or more alignment features extending away from a main lateral surface. Each of the alignment features includes a first lateral surface that is vertically offset from the main lateral surface, and first and second vertical sidewalls that extend between the first lateral surface and the main lateral surface. An epitaxy blocker is formed on the first and second vertical sidewalls of each alignment feature. A type III-V semiconductor regrown layer is epitaxially grown on a portion of the semiconductor wafer that includes the one or more alignment features. The epitaxy blocker prevents the type III-V semiconductor regrown layer from forming on the first and second vertical sidewalls of the one or more alignment features.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: March 20, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Simone Lavanga, Uttiya Chowdhury, Mattia Capriotti
  • Patent number: 9905811
    Abstract: A method of manufacturing a joined body, including: covering a first area and a second area of a first substrate with a sheet of resin in uncured state; separating a part of the sheet covering the second area from the first substrate, the separating performed after the covering; and joining the first substrate with a second substrate by arranging the second substrate to face the first substrate with a part of the sheet covering the first area between the first substrate and the second substrate, and curing the resin in the part of the sheet covering the first area, the joining performed after the separating. In the method, during the separating, a phase difference ? between stress and strain in the part of the sheet covering the second area is no greater than 48 degrees.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: February 27, 2018
    Assignee: JOLED INC.
    Inventor: Hiroko Okumura
  • Patent number: 9905588
    Abstract: A display panel and a method for manufacturing the display panel are discussed. The display panel includes a substrate; an active layer on the substrate; and a passivation layer on the active layer, wherein the active layer includes a channel part, a first electrode connection part and a second electrode connection part on opposite sides of the channel part in a first direction, and a first taper part and a second taper part on opposite sides of the channel part in a second direction crossing the first direction, and wherein a carrier concentration of each of the first taper part and the second taper part is different from those of the channel part, the first electrode connection part and the second electrode connection part.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: February 27, 2018
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Ki Woo Kim, Jung Hyun Kim, Jong Seuk Kang, Hyung Jin Bang, Yoon Ji Choi, Min Ho Shin, Choong Koo Park
  • Patent number: 9905632
    Abstract: The light-emitting unit includes a first light-emitting element and a second light-emitting element over an insulating surface. The first light-emitting element includes a first electrode, a second electrode, and a layer containing a light-emitting organic compound interposed between the first and second electrodes. An edge portion of the first electrode is covered with a first insulating partition wall. The second light-emitting element includes a third electrode, a fourth electrode, a light-emitting organic compound interposed between the third and fourth electrodes. The first and third electrodes are formed from the same layer having a property of transmitting light emitted from the light-emitting organic compound. The second and fourth electrodes are formed from the same layer. The second electrode intersects with the edge portion of the first electrode with the first partition wall interposed therebetween, whereby the second electrode and the third electrode are electrically connected to each other.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: February 27, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9893198
    Abstract: A method for manufacturing a thin film transistor (TFT) which includes a gate, a gate insulation layer, a channel layer, an etching stopping layer, a source, and a drain. The gate is formed on a substrate. The gate insulation layer covers the gate and the substrate. The channel layer is formed on the gate insulation layer to correspond with the gate. The etching stopping layer is formed on a surface of the channel layer. The channel layer and the etching stopping layer are formed in a same photo etching process.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: February 13, 2018
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Kuo-Lung Fang, Yi-Chun Kao, Hsin-Hua Lin, Po-Li Shih, Chih-Lung Lee
  • Patent number: 9893235
    Abstract: A light emitting device is provided a transmissive substrate; a first pattern portion including a protrusions; a second pattern portion including a concaves having a width smaller than a width of each protrusion; a light emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer and an active layer, under the transmissive substrate; a first electrode under the first conductive semiconductor layer; a reflective electrode layer under the second conductive semiconductor layer; a second electrode under the reflective electrode layer; a first connection electrode under the first electrode; a second connection electrode under the second electrode; and an insulating support member around the first electrode and the first connection electrode and around the second electrode and the second connection electrode. A transmissive resin layer is on the transmissive substrate and an insulating layer is between the insulating support member and the reflective electrode layer.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: February 13, 2018
    Assignee: LG INNOTEK CO., LTD
    Inventors: Pil Geun Kang, Hee Seok Choi, Seok Beom Choi, Ju Won Lee, Deok Ki Hwang, Young Ju Han
  • Patent number: 9887175
    Abstract: A lighting device includes a plurality of organic EL light-emitting devices having organic EL elements, and a plurality of LEDs. The LEDs are provided as point light sources, and the organic EL light-emitting devices are provided as surface light sources. Using an LED which emits blue light and an organic EL element which emits yellow light, white light can be obtained. The LEDs are provided on the back side or the front side of the organic EL light-emitting devices so that light from the LEDs pass between the two organic EL light-emitting devices. Accordingly, light can be extracted from the LEDs without allowing the LED light to pass through the organic EL elements. Further, the organic EL element is sealed by two substrates and a sealant, whereby deterioration due to moisture or oxygen can be prevented.
    Type: Grant
    Filed: December 27, 2011
    Date of Patent: February 6, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomoya Aoyama, Satoshi Seo
  • Patent number: 9887378
    Abstract: An organic light-emitting display apparatus includes a substrate comprising pixels, each of which comprises a first sub-pixel, a second sub-pixel, and a third sub-pixel, and a plurality of pixel electrodes independently formed for respective sub-pixels; a first common layer commonly formed on the pixels; first lines covering first sub-pixels arranged in a first direction, wherein the first lines comprise a first organic light-emitting layer; a plurality of second lines covering second sub-pixels arranged in the first direction, wherein the second lines comprise a second organic light-emitting layer differing from the first organic light-emitting layer; a second common layer commonly formed on the plurality of pixels, wherein the second common layer comprises a third organic light-emitting layer differing from the first organic light-emitting layer and the second organic light-emitting layer; a third common layer commonly formed on the pixels; and an opposite electrode commonly formed on the pixels.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: February 6, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventor: Seung-Wook Chang
  • Patent number: 9825253
    Abstract: An organic light-emitting apparatus includes a lower substrate comprising a display area and a peripheral area around the display area; a first insulating layer on the display area and the peripheral area of the lower substrate, wherein a plurality of penetration holes are formed in the first insulating layer in the peripheral area; an upper substrate on the lower substrate; and a sealant in the plurality of penetration holes bonding the lower substrate to the upper substrate.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: November 21, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sung-Ho Cho, Hyun-Young Kim, Il-Ryong Cho
  • Patent number: 9818692
    Abstract: Devices and systems comprising high current/high voltage GaN semiconductor devices are disclosed. A GaN die, comprising a lateral GaN transistor, is sandwiched between an overlying header and an underlying composite thermal dielectric layer. Fabrication comprises providing a conventional GaN device structure fabricated on a low cost silicon substrate (GaN-on-Si die), mechanically and electrically attaching source, drain and gate contact pads of the GaN-on-Si die to corresponding contact areas of conductive tracks of the header, then entirely removing the silicon substrate. The exposed substrate-surface of the epi-layer stack is coated with the composite dielectric thermal layer. Preferably, the header comprises a ceramic dielectric support layer having a CTE matched to the GaN epi-layer stack. The thermal dielectric layer comprises a high dielectric strength thermoplastic polymer and a dielectric filler having a high thermal conductivity.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: November 14, 2017
    Assignee: GaN Systems Inc.
    Inventors: John Roberts, Greg P. Klowak, Cameron McKnight-MacNeil
  • Patent number: 9728549
    Abstract: A semiconductor device may include a cell gate conductive pattern in a cell array area that extends to a step area, a cell vertical structure in the cell array area that extends through the cell gate conductive pattern, a cell gate contact structure on the cell gate conductive pattern in the step area, a cell gate contact region in the cell gate conductive pattern and aligned with the cell gate contact structure, a first peripheral contact structure spaced apart from the cell gate conductive pattern, a second peripheral contact structure spaced apart from the first peripheral contact structure, a first peripheral contact region under the first peripheral contact structure, and a second peripheral contact region under the second peripheral contact structure. The cell gate contact region may include a first element and a remainder of the cell gate conductive pattern may not substantially include the first element.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: August 8, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jang-Gn Yun, Sunghoi Hur, Jaesun Yun, Joon-Sung Lim