Abstract: A method of forming an electrically insulating barrier between a source contact and a drain contact of a transistor device including an electrically insulating layer disposed atop a semi-conductive layer, and an electrically conductive layer disposed atop the electrically insulating layer, the source contact and the drain contact extending from the electrically conductive layer through the electrically insulating layer to the semi-conductive layer, the method including disposing a hardmask layer atop the electrically conductive layer, disposing a photoresist layer atop the hardmask layer, performing a photolithography process to form a trench in the hardmask layer to expose an underlying portion of the electrically conductive layer spanning between the source contact and the drain contact, and performing an ion implantation process, wherein an ion beam formed of ionized oxygen atoms is directed into the trench to oxidize the exposed portion of the electrically conductive layer.

Abstract: Techniques for forming quantum circuits, including connections between components of quantum circuits, are presented. A trench can be formed in a dielectric material, by removing a portion of the dielectric material and a portion of conductive material layered on top of the dielectric material, to enable creation of circuit components of a circuit. The trench can define a regular nub or compensated nub to facilitate creating electrical leads connected to the circuit components on a nub. The compensated nub can comprise recessed regions to facilitate depositing material during evaporation to form the leads. For compensated nub implementation, material can be evaporated in two directions, with oxidation performed in between such evaporations, to contact leads and form a Josephson junction. For regular nub implementation, material can be evaporated in four directions, with oxidation performed in between the third and fourth evaporations, to contact leads and form a Josephson junction.

Abstract: This planar light source device has a pair of substrates, a pair of irradiation plates disposed between the pair of substrates, and a plurality of light emission devices disposed on one or both of the pair of substrates. In a cross-section of the light emission devices in a direction perpendicular to the irradiation plates through an optical axis, the luminosity of light emitted in a 7.0° direction when 0° is the optical axis direction and the luminosity of light emitted in a (tan?1(t/L))° (where t represents the gap between the irradiation plates, and L represents the gap, in a direction along the pair of irradiation plates, from the surface of a light emission device disposed on one of the substrates to an end part of the other-substrate-side irradiation plate) direction or a (tan?1(t/2L))° direction satisfy a prescribed relationship.

Abstract: An electrical device includes a first terminal structured to electrically connect to a power source; a second terminal structured to electrically connect to a load; a voltage sensor electrically connected to a point between the first and second terminals and being structured to sense a voltage at the point between the first and second terminals; a switch electrically connected between the first terminal and the second terminal; and a control unit structured to detect a power quality event in the power flowing between the first and second terminals based on the sensed voltage and to control a state of the switch based on the detected power quality event.

Abstract: A method may include forming in a substrate a first array of a first material of first linear structures, interspersed with a second array of a second material, of second linear structures, the first and second linear structures elongated along a first axis. The method may include generating a chop pattern in the first layer, comprising a third linear array, interspersed with a fourth linear array. The third and fourth linear arrays may be elongated along a second axis, forming a non-zero angle of incidence with respect to the first axis. The third linear array may include alternating portions of the first and second material, while the fourth linear array comprises an array of cavities, arranged within the patterning layer. The method may include elongating a first set of cavities along the first axis, to form a first set of elongated cavities bounded by the first material.

Abstract: An integrated circuit is described. The integrated circuit includes a laterally diffused metal oxide semiconductor (LDMOS) transistor. The LDMOS is on a first surface of an insulator layer of the integrated circuit. The LDMOS transistor includes a source region, a drain region, and a gate. The LDMOS transistor also includes a secondary well between the drain region and the gate. The secondary well has an opposite polarity from the drain region. The LDMOS transistor further includes a backside device on a second surface opposite the first surface of the insulator layer.

Abstract: A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.

Abstract: A semiconductor wafer serving as a treatment target has a stack structure in which a high-dielectric-constant gate insulating film is formed on a silicon base material with an interface layer film of silicon dioxide sandwiched therebetween, and a metal gate electrode containing fluorine is further formed thereon. A heat treatment apparatus radiates flash light from a flash lamp to the semiconductor wafer in an atmosphere containing hydrogen to carry out heating treatment for an extremely short period of time of 100 milliseconds or less. As a result, diffusion of nitrogen contained in the metal gate electrode is inhibited, at the same time, only the fluorine is diffused from the high-dielectric-constant gate insulating film to an interface between the interface layer film and the silicon base material to reduce an interface state, and reliability of the gate stack structure can be improved.

Abstract: Some embodiments include an integrated assembly having digit lines extending along a first direction, and rails over the digit lines. The rails include semiconductor-material pillars alternating with intervening insulative regions. The rails have upper, middle and lower segments. A first insulative material is along the upper and lower segments of the rails. A second insulative material is along the middle segments of the rails. The second insulative material differs from the first insulative material in one or both of thickness and composition. Conductive gate material is along the middle segments of the rails and is spaced from the middle segments by the second insulative material. Channel regions are within the middle segments of the pillars, upper source/drain regions are within the upper segments of the pillars and lower source/drain regions are within the lower segments of the pillars. Some embodiments include methods of forming integrated assemblies.

Abstract: A self-limiting etch is used to provide a semiconductor base located between a semiconductor substrate and a semiconductor fin. The semiconductor base has an upper portion, a lower portion and a midsection. The midsection has a narrower width than the lower and upper portions. A bottom source/drain structure is grown from surfaces of the semiconductor substrate and the semiconductor base. The bottom source/drain structure has a tip region that contacts the midsection of the semiconductor base. The bottom source/drain structures on each side of the semiconductor fin are in close proximity to each other and they have increased volume. Reduced access resistance may also be achieved since the bottom source/drain structure has increased volume.

Abstract: A semiconductor device includes: a substrate having active regions defined by a device isolation region; a conductive line extending in a direction on the active regions; insulating liners on both sidewalls of a lower portion of the conductive line that contacts with the active regions; spacers that are apart from the insulating liners in a direction perpendicular to a surface of the substrate and sequentially formed on both sidewalls of an upper portion of the conductive line; a blocking layer arranged at a spacing between a spacer located in the middle of the spacers and the insulating liners and in a recess portion recessed from one end of the spacer located in the middle of the spacers toward the conductive line; and conductive patterns arranged on the active regions on both sides of the spacers.

Abstract: The wafer-level manufacturing method makes possible to manufacture ultrathin optical devices such as opto-electronic modules. A clear encapsulation is applied to an initial wafer including active optical components and a wafer-size substrate. Thereon, a photostructurable spectral filter layer is produced which defines apertures. Then, trenches are produced which extend through the clear encapsulation and establish sidewalls of intermediate products. Then, an opaque encapsulation is applied to the intermediate products, thus filling the trenches and producing aperture stops. Cutting through the opaque encapsulation material present in the trenches, singulated optical modules are produced, wherein side walls of the intermediate products are covered by the opaque encapsulation material. The wafer-size substrate can be attached to a rigid carrier wafer during most process steps.

Abstract: A semiconductor device and method includes forming a conductive post on a die; coupling a test probe to the conductive post with solder; and etching the solder and the conductive post with a plurality of etching processes, the plurality of etching processes including a first etching process, the first etching process comprising etching the conductive post with a nitric-based etchant.

Abstract: A light emitting device includes a substrate, an adhesion layer, a micro light emitting device (?LED), a first conductive layer, and a second conductive layer. A light emitting surface of the ?LED is away from the substrate. The ?LED includes a first semiconductive layer, a second semiconductive layer, a tether layer, a first electrode, and a second electrode. The tether layer covers a portion of sidewalls of the first semi-conductive layer, a portion of a bottom surface of the first semi-conductive layer, sidewalls of the second semiconductive layer, and a portion of a bottom surface of the second semiconductive layer. The first electrode and the second electrode are respectively electrically connected to the first semiconductive layer and the second semiconductive layer. The first conductive layer and the second conductive layer are respectively electrically connected to the first electrode and the second electrode.

Abstract: A display device may include a substrate having a first pixel area, a first electrode on the substrate; a passivation layer between the substrate and the first electrode, a second electrode on the first electrode, and an organic emission layer between the first electrode and the second electrode. The first pixel area may include an emission area and a non-emission area surrounded by the emission area.

Abstract: Methods and apparatus are provided to improve the yield rate of LED packaging using LED flip chips. In one novel aspect, extended pads made of sintered silver are disposed on the cathode and the anode of the LED flip chip. The thickness of the extended pad is from about 25 ?m to about 200 ?m. In another embodiment, the LED flip chip further comprises a phosphor layer such that the LED flip chip emits white light. In another novel aspect, the LED flip chip with extended pads made of sintered silver is produced at the wafer level. The wafer level process involves applying sintering silver pastes to the cathode and the anode of each LED flip chip formed on the wafer and sintering the wafer at a temperature about 180° C. to about 240° C. for about two hours. The wafer is cut to individual LED flip chips with extended sintered silver pads.

Abstract: A semiconductor package structure includes a first conductive structure, a second conductive structure, a first semiconductor component, a second semiconductor component and a first encapsulant. The first semiconductor component is disposed on the first conductive structure. The first conductive structure includes a first redistribution layer. The second semiconductor component is disposed on the second conductive structure. The second conductive structure includes a second redistribution layer, and the first conductive structure is electrically connected to the second conductive structure. The first encapsulant covers the first semiconductor component and the first conductive structure. A lateral surface of the first conductive structure and a lateral surface of the first encapsulant are non-coplanar.

Abstract: CMOS Ultrasonic Transducers and processes for making such devices are described. The processes may include forming cavities on a first wafer and bonding the first wafer to a second wafer. The second wafer may be processed to form a membrane for the cavities. Electrical access to the cavities may be provided.

Abstract: Devices, structures, materials and methods for carbon enabled vertical light emitting transistors (VLETs) and light emitting displays (LEDs) are provided. In particular, architectures for vertical polymer light emitting transistors (VPLETs) for active matrix organic light emitting displays (AMOLEDs) and AMOLEDs incorporating such VPLETs are described. Carbon electrodes (such as from graphene) alone or in combination with conjugated light emitting polymers (LEPs) and dielectric materials are utilized in forming organic light emitting transistors (OLETs). Combinations of thin films of ionic gels, LEDs, carbon electrodes and relevant substrates and gates are utilized to construct LETs, including heterojunction VOLETs.

Abstract: A display device includes a pixel connected to a data line, a data pad connected to the data line, and a first test area. The first test area includes a test control line transmitting a test control signal, a test signal line transmitting a test signal, and a first switch connected to the data pad. The first switch includes a gate electrode connected to the test control line, first and second semiconductor layers overlapping the gate electrode, a source electrode connected to the first and second semiconductor layers, and a drain electrode spaced from the source electrode and connected to the first and second semiconductor layers. The source electrode and the drain electrode are connected to the test signal line and data pad, respectively. One of the first or second semiconductor layers includes an oxide semiconductor and the other of the first or second semiconductor layer includes a silicon-based semiconductor.