Abstract: An electronic device includes: a first insulation layer and a first conductive pillar. The first insulation layer has a first surface and a second surface opposite to the first surface, and the first conductive pillar comprises a first portion and a second portion. The first portion of the first conductive pillar is surrounded by the first insulation layer. The second portion of the first conductive pillar is disposed on the first surface of the first insulation layer. A height of the second portion of the first conductive pillar is equal to or greater than 10% of a height of the first portion of the conductive pillar.

Abstract: A light emitting diode apparatus including a substrate, a plurality of light emitting diodes regularly arranged on the substrate and configured to emit ultraviolet (UV) light, the light emitting diodes including first, second, and third sub-light emitting diodes, a plurality of phosphor layers disposed on the light emitting diodes and to convert the wavelength of light emitted from the light emitting diodes, the phosphor layers including first, second, and third phosphor layers disposed on the first, second, and third sub-light emitting diodes, respectively, and a control unit configured to supply power to the light emitting diodes, in which the phosphor layers are spaced apart from each other by a blocking region, and the control unit is configured to cause at least a portion of the light emitting diodes to emit light.

Abstract: A display apparatus including a panel substrate including a TFT drive circuit for active matrix driving, a plurality of light emitting diodes, and an anisotropic conductive film electrically connecting the light emitting diodes to the panel substrate, in which the anisotropic conductive film includes an adhesive organic insulation material and conductive particles dispersed in the adhesive organic insulation material.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes device fins formed on a substrate; fill fins formed on the substrate and disposed among the device fins; and gate stacks formed on the device fins and the fill fins. The fill fins include a first dielectric material layer and a second dielectric material layer deposited on the first dielectric material layer. The first and second dielectric material layers are different from each other in composition.

Abstract: A method for manufacturing an active matrix substrate including a thin film transistor for each pixel, and a first electrode and a first wiring line for touchscreen panel function includes: forming a transparent electrically conductive film on an interlayer insulating layer and within a first contact hole; forming, on a portion of the transparent electrically conductive film, an upper wiring portion to become an upper layer of the first wiring line; patterning the transparent electrically conductive film to make a pixel electrode and form a lower wiring portion to become a lower layer of the first wiring line; forming a dielectric layer covering the pixel electrode and the first wiring line and having a second contact hole through which a portion of the first wiring line is exposed; and forming a common electrode which is electrically connected to the first wiring line within the second contact hole.

Abstract: A MEMS component including a first substrate having at least one first insulating layer and a first metallic coating on a first side; and including a second substrate having at least one second insulating layer and a second metallic coating on a second side, the second substrate including a micromechanical functional element, which is connected electroconductively to the second metallic layer. The first side and the second side are positioned on each other, the first insulating layer and the second insulating layer being interconnected, and the first metallic coating and the second metallic coating being interconnected. A method for manufacturing a MEMS component is also described.

Abstract: A semiconductor device includes a semiconductor device and a semiconductor fin on the semiconductor substrate, in which the semiconductor fin has a fin isolation structure at a common boundary that is shared by the two cells. The fin isolation structure has an air gap extending from a top of the semiconductor fin to a stop layer on the semiconductor substrate. The air gap divides the semiconductor fin into two portions of the semiconductor fin. The fin isolation structure includes a dielectric cap layer capping a top of the air gap.

Abstract: Systems and methods for forming a low contact resistance nanowire transistor are described. The transistor includes a gate formed over a substrate including a gate conductor. Gate spacers are formed on sides of the gate. At least one semiconductor nanowire is formed through the gate such that the at least one semiconductor nanowire extends through the gate conductor and the gate spacers and into source and drain regions grown from surfaces of the at least one semiconductor nanowire adjacent to sides of the gate to increase the surface area of the source drain region contacting the semiconductor nanowire.

Abstract: A light emitting module includes: a plurality of light emitting elements each having a primary light emitting surface and a lateral surface; a plurality of wavelength conversion members arranged respectively on the primary light emitting surfaces of the plurality of light emitting elements; and a lightguide plate having a first primary surface and a second primary surface and arranged continuously on the plurality of wavelength conversion members so that the second primary surface faces the plurality of wavelength conversion members, wherein the lightguide plate includes a plurality of recessed portions located on the second primary surface, and a lateral surface of at least one of the plurality of wavelength conversion members is partially in contact with an inner lateral surface of at least one of the plurality of recessed portions.

Abstract: The present disclosure discloses a backplane for an organic light emitting display device, a method for fabricating the same, and an organic light emitting display apparatus. The backplane includes a substrate on which a wiring structure and a thin film transistor are provided, wherein the wiring structure includes an initializing voltage input line which is provided in the same layer and made of the same material as electrodes of the thin film transistor.

Abstract: Provided are apparatuses and methods for performing deposition and etch processes in an integrated tool. An apparatus may include a plasma processing chamber that is a capacitively-coupled plasma reactor, and the plasma processing chamber can include a showerhead that includes a top electrode and a pedestal that includes a bottom electrode. The apparatus may be configured with an RF hardware configuration so that an RF generator may power the top electrode in a deposition mode and power the bottom electrode in an etch mode. In some implementations, the apparatus can include one or more switches so that at least an HFRF generator is electrically connected to the showerhead in a deposition mode, and the HFRF generator and an LFRF generator is electrically connected to the pedestal and the showerhead is grounded in the etch mode.

Abstract: A method of manufacture and structure for a monolithic single chip single crystal device. The method can include forming a first single crystal epitaxial layer overlying the substrate and forming one or more second single crystal epitaxial layers overlying the first single crystal epitaxial layer. The first single crystal epitaxial layer and the one or more second single crystal epitaxial layers can be processed to form one or more active or passive device components. Through this process, the resulting device includes a monolithic epitaxial stack integrating multiple circuit functions.

Abstract: A heterostructure, such as a group III nitride heterostructure, for use in an optoelectronic device is described. The heterostructure can include a sacrificial layer, which is located on a substrate structure. The sacrificial layer can be at least partially decomposed using a laser. The substrate structure can be completely removed from the heterostructure or remain attached thereto. One or more additional solutions for detaching the substrate structure from the heterostructure can be utilized. The heterostructure can undergo additional processing to form the optoelectronic device.

Abstract: An embodiment relates to a method for manufacturing a semiconductor device. The method includes providing a semiconductor body including a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type interposed between the first semiconductor region and a first surface of the semiconductor body. The method further includes forming a first contact layer over the first surface of the semiconductor body. The first contact layer forms a direct electrical contact to the second semiconductor region. The method further includes forming a contact trench extending into the semiconductor body by removing at least a portion of the second semiconductor region. The method further includes forming a second contact layer in the contact trench. The second contact layer is directly electrically connected to the semiconductor body at a bottom side of the contact trench.

Abstract: A transistor device includes a plurality of drain fingers that are elongate in a first dimension, a plurality of source fingers that are elongate in the first dimension and interleaved with the plurality of drain fingers, one or more drain contact bars extending over a first set of the plurality of drain fingers and a first set of the plurality of source fingers in a second dimension that is orthogonal to the first dimension, and one or more source contact bars extending over a second set of the plurality of drain fingers and a second set of the plurality of source fingers in the second dimension.

Abstract: A semiconductor structure that includes a resistor that is located within an interconnect dielectric material layer of an interconnect level is provided. The resistor includes a diffusion barrier material that is present at a bottom of a feature that is located in the interconnect dielectric material layer. In some embodiments, the resistor has a topmost surface that is located entirely beneath a topmost surface of the interconnect dielectric material layer. In such an embodiment, the resistor is provided by removing sidewall portions of a diffusion barrier liner that surrounds a metal-containing structure. The removal of the sidewall portions of the diffusion barrier liner reduces the parasitic noise that is contributed to the sidewall portions of a resistor that includes such a diffusion barrier liner. Improved precision can also be obtained since sidewall portions may have a high thickness variation which may adversely affect the resistor's precision.

Abstract: A method for manufacturing a semiconductor device includes growing a first strained semiconductor layer on a substrate, the first strained semiconductor layer having a first type of strain, wherein the substrate comprises a first crystalline orientation at a top surface of the substrate, forming at least one trench in the substrate, wherein exposed sidewalls of the at least one trench have a second crystalline orientation different from the first crystalline orientation, growing a buffer layer in the at least one trench from the exposed sidewalls of the trench, and growing a second strained semiconductor layer on the buffer layer, the second strained semiconductor layer having a second type of strain, wherein the first type of strain is different from the second type of strain.

Abstract: A method of forming an electrically insulating barrier between a source contact and a drain contact of a transistor device including an electrically insulating layer disposed atop a semi-conductive layer, and an electrically conductive layer disposed atop the electrically insulating layer, the source contact and the drain contact extending from the electrically conductive layer through the electrically insulating layer to the semi-conductive layer, the method including disposing a hardmask layer atop the electrically conductive layer, disposing a photoresist layer atop the hardmask layer, performing a photolithography process to form a trench in the hardmask layer to expose an underlying portion of the electrically conductive layer spanning between the source contact and the drain contact, and performing an ion implantation process, wherein an ion beam formed of ionized oxygen atoms is directed into the trench to oxidize the exposed portion of the electrically conductive layer.

Abstract: Techniques for forming quantum circuits, including connections between components of quantum circuits, are presented. A trench can be formed in a dielectric material, by removing a portion of the dielectric material and a portion of conductive material layered on top of the dielectric material, to enable creation of circuit components of a circuit. The trench can define a regular nub or compensated nub to facilitate creating electrical leads connected to the circuit components on a nub. The compensated nub can comprise recessed regions to facilitate depositing material during evaporation to form the leads. For compensated nub implementation, material can be evaporated in two directions, with oxidation performed in between such evaporations, to contact leads and form a Josephson junction. For regular nub implementation, material can be evaporated in four directions, with oxidation performed in between the third and fourth evaporations, to contact leads and form a Josephson junction.

Abstract: This planar light source device has a pair of substrates, a pair of irradiation plates disposed between the pair of substrates, and a plurality of light emission devices disposed on one or both of the pair of substrates. In a cross-section of the light emission devices in a direction perpendicular to the irradiation plates through an optical axis, the luminosity of light emitted in a 7.0° direction when 0° is the optical axis direction and the luminosity of light emitted in a (tan?1(t/L))° (where t represents the gap between the irradiation plates, and L represents the gap, in a direction along the pair of irradiation plates, from the surface of a light emission device disposed on one of the substrates to an end part of the other-substrate-side irradiation plate) direction or a (tan?1(t/2L))° direction satisfy a prescribed relationship.