Abstract: A method and apparatus for determining and selecting configuration options and settings of circuit boards used in a computer system is disclosed. The options and settings are placed in a file according to a given format, at which time the system determines if non-conflicting use of the common system resources is possible. If so, these option and setting parameters are used to configure the circuit boards.

Abstract: A method of conveniently making a selection from a set of options available in a computer program is described. As successive letters which make up the proposed selection are entered, successively smaller lists of options corresponding to the entered letters are displayed. At any point, the user makes a selection by moving a cursor to a desired selection and pressing a button or key to indicate that the selection has been made.

Abstract: A distributed method for arbitrating access to a common bus in a multiple processor environment is described. This method provides for fairness where multiple processors are vying for access to a global memory. An apparatus for arbitrating access to a common bus in a multiple processor environment is also described. This apparatus provides for priority determination of each processor upon system reset and provides for fairness where multiple processors are vying for access to a global memory.

Abstract: The present invention relates to a method and apparatus to determine whether a user is authorized to utilize a data communication network, and more particularly a terminal machine in the network. Data having a predetermined number of bits are read out from a relatively large random number memory, containing previously stored data, by using key data to address said bits at the terminal machine. The addressed data are used as new key data and data each having a predetermined number of bits are repeatedly read from the data in the random number memory to form identification data on the basis of the old and new key data in each cycle. In such manner, there are formed identification data unequivocally determined in accordance with the key data and having high security or confidentiality.

Abstract: A shared power controller for a rack of interface devices which are shared among a plurality of processor units. The shared power controller may be commanded into a power up mode by any connected central processor via its system power interface. A power down of a connected rack of interface units may, however, only be effected when all the connected CPU units enter a power down mode. A system power controller provides both remote and local operation such that diagnosis and analysis of problems may be effected locally at each rack of input/output devices.

Abstract: An interface circuit for use between a radio control transmitter equipped with joysticks and a standard serial input port of a personal type computer. The interface circuitry includes a microcontroller operated as a reformatter for signals received from the remote control transmitter and a transistorized converter circuit connected between the output of the microcontroller and computer to convert the voltage level of signals output from the microcontroller in reformatted form.

Abstract: The invention is in the realm of an information processing system including a central unit which includes several processors sending requests to several processors sending requests to several memories via an input interconnection and receiving responses from those memories via an output interconnection. To simplify the input interconnection when the number of processors and memories increases, a ring of stations equipped with a register is used. A request given by a processor is loaded into a station when that station is free or becomes free, If not the ring functions a fed back shift register. A station becomes free when the request contained in the station downstream is accepted by a memory. An analogous device can be used for the output interconnection. A notable application is vector processing.

Abstract: A parallel to serial converter for convering incoming parallel, byte sized, data supplied at a first data rate to single bit serial data includes a shift register in which several bytes of the incoming data are stored simultaneously and thereafter serially transmitted therefrom. The parallel to serial converter includes latching devices in which the incoming data bytes are stored prior to being transferred to the shift register. Since successively arriving bytes of data are stored in successively selected ones of the latching devices, the data rate (device speed) of the latches is permitted to be only a fraction of the first data rate associated with the incoming bytes of data resulting in a fast, yet inexpensive, circuit.

Abstract: A data processor comprises a plurality of registers 1 (registers a to d), a plurality of data saving stack memory devices 2 coupled to the registers 1 for exclusive use thereof, respectively, and an instruction decoder for decoding instructions for controlling the registers 1 and the data saving stack memory devices 2 in accordance with the result of the instruction decoding. In response to an instruction "PUSH", the contents of the registers 1 (registers a to d) are selectively saved to the data saving stack memory device 2. In response to a instruction "POP", the contents of the data saving stack memory devices 2 are selectively restored to the registers 1 (registers a to d). Each of the instructions "PUSH" and "POP" has a field for indicating need or needlessness of the saving and restoration for each of the registers 1 and each of the data saving memories 2.

Abstract: A bus controller, operable to grant access to a bus structure for communication between a number of individual processor modules interconnected by the bus to form a multiprocessor system, is also operable to determine the number of processors connected to the bus. The bus controller, in round-robin fashion, sequentially grants each processor access to the bus by commanding the processor to send data. The processor responds either by sending data in synchronism with a data clock supplied by the bus controller or, if no data is to be sent, responds with a no acknowledgment (NAK) signal. Initially, and periodically, the bus controller checks to determine the number of processors by, beginning with the highest identifying numbered processor, sending to that processor a send command, and looking for a response either in the form of data being sent or a NAK signal.

Abstract: A multi-processor system and method arranged, in one embodiment, as an image and graphics processor. The multiprocessor system includes several individual processors all having communication links to several memories. Additional instruction memories are dedicated individually as cache memories to particular processors so that the processors can function in the multiple instruction, multiple data (MIMD) mode. When the processors function in the single instruction, multiple data mode (SIMD) the dedicated memories are reassigned for access by all of the processors for data. A crossbar switch serves to establish the processor memory links. The entire image processor, including the individual processors, the crossbar switch and the memories, is contained on a single silicon chip.

Abstract: A multiprocessor type time varying image encoding system having a plurality of digital signal processor (DSP) modules (DMM's) connected in parallel, each DMM having a DSP, a local memory and an interrupt control unit, a plurality of common memories for storing data which is being processed, parameters, etc., an input frame memory which enables reading and writing operations to be executed asynchronously, a combination of a task control unit and a task table for distributing tasks to the DMM's, a plurality of independent common buses, and a combination of a bus control unit and a bus control table for bus sharing control.

Abstract: In a computer system including a main memory and an expanded memory for expanding said main memory logically, a program operating on a virtual memory space, which is managed by the virtual memory management of an operating system, for managing the input/output of the data on an external storage device by using an I/O buffer has a function to manage the I/O buffer secured on the expanded memory, so that the I/O processing for the external storage memory may be reduced by either saving the data, if necessary, of the I/O buffer on the virtual space into the I/O buffer on the expanded memory or restoring the same to the I/O buffer on the virtual space, whereby the I/O buffers can be efficiently utilized.

Abstract: The set-prediction cache memory system comprises an extension of a set-associative cache memory system which operates in parallel to the set-associative structure to increase the overall speed of the cache memory while maintaining its performance. The set prediction cache memory system includes a plurality of data RAMs and a plurality of tag RAMs to store data and data tags, respectively. Also included in the system are tag store comparators to compare the tag data contained in a specific tag RAM location with a second index comprising a predetermined second portion of a main memory address.

Abstract: A test circuit for testing a programmable array of a microprocessor including an instruction register for receiving an instruction signal from a data bus in response to a control signal and for outputting the received instruction signal to output lines, and a programmable logic array having a plurality of NAND circuits each forming a conductive path between first and second terminals when a predetermined instruction signal is received thereby from the register. Each of the NAND circuits includes a first terminal, a second terminal and a plurality of MOSFETs each having a first, a second and a gate electrode with the gate electrode coupled to an output line of the instruction register, and with the first and second electrodes being connected in series between the respective first and second terminals.

Abstract: A data processing system provides annotation of a document through an electronic tablet, a keyboard and an audio assembly. An annotatable document is generated from a window of a multiwindow support program running independently of the annotation program in the data processing system. For each window of the multiwindow program, a working document is generated and is annotatable by the annotation program and apparatus. An annotatable document is also generated from the whole screen view of overlapping windows produced during execution of the multiwindow support program. Annotated working documents may be subsequently stored in and thereafter retrieved from the database of the multiwindow support program.

Abstract: A data processing system is described which contains a first program for enabling the operation of interactive second and third programs, the second program requiring program parameters and file data from the third program in order to operate in conjunction therewith. The first program displays a menu of functions performable by the second program when it is run in conjunction with the third program. The first program responds to a user-selected menu function by employing the method of: extracting from the third program, parameters required for operation of the second program and placing such parameters in a format usable by the second program; constructing input files for the second program which include command listings required to perform a user-selected menu function, and indications of program sequences to be operated upon by the menu function; and executing the selected menu function by employing the command listings to enable automatic interactive operation of the second and third programs.

Abstract: Read-write buffer apparatus is provided for reducing the time necessary to resolve read conflicts during normal and block mode read requests. Additionally, the read-write buffer apparatus provides a means for gathering non-sequential write requests in an internal write buffer, thus reducing the frequency of a buffer full condition. The enhanced read-write buffer apparatus minimizes CPU wait states, while increasing the CPU processing rate and improves overall data processing system throughput.

Abstract: A floating point processor (10) is provided having a multiplier (48) and an ALU (54) for performing arithmetic calculations simultaneously. The output of the multiplier (48) and ALU (54) are stored in a product register (64) and a sum register (66), respectively. Multiplexers (40,42,44,46) are provided at the inputs to the multiplier (48) and the ALU (54). The multiplexers choose between data in input registers (32,34), product and sum registers (64,66), and an output register (76). Since the multiplier (48) and ALU (54) operate simultaneously, and since the outputs of the multiplier (48) and ALU (54) are available to the multiplexers (40-46), product of sums calculations and sum of products calculations may be performed rapidly. An input stage (12) uses a temporary register (18) to store data from a data bus on the first clock edge, and configuration logic (28) for directing data from the data bus and the temporary register (18) to the input registers (32,34) on a second clock edge.

Abstract: A system for testing certain attributes (i.e., performance and usability) of an interactive system program. A memory device stores data representative of interactive commands generated by a user. A device is also provided for executing an emulator overlay connected to the memory device for receiving data therefrom and modifying it in subsequent transmission. The emulator overlay has a time measuring device associated with it for determining performance of an interactive system program. A device is also provided for storing and executing an interactive system program connected to the emulator overlay. Finally, another memory device is provided for storing the data representative of system program performance. The system is capable of capturing human factors data, including screen images and associated keystrokes entered during a user session, measuring time intervals between the screen images and keystrokes, and providing such data to a system analyst to determine usability of host computer resident software.