Abstract: A computer peripheral device incorporating a multi-task control device which is extremely useful for such programs controlling the microcomputer system. In particular, the multi-task control device effectively controls a plurality of tasks executed by the CPU by using means other than the CPU including such means for controlling operations needed for comparing priority orders between a plurality of tasks, and the other means for generating interrupt operations from this control device against the CPU needed for switching tasks being executed in accordance with the result of the priority comparative operations.

Abstract: A software engineering tool is disclosed which enables the efficiency and performance of a program design to be evaluated prior to the time the program is written into code. Every possible path that can be followed in the implementation of the program is identified, and its length is measured. From this information, reports are generated which point out the longest paths in the program and sources of potential performance problems. In addition, weights which identify relative complexities or performance timings can be assigned to individual modules in the program, and form the basis of other reports which indicate timing performance. The user is provided with the opportunity to alter the weights assigned to modules, and thereby determine the effect which different weights have on the overall performance of the program.

Abstract: In a pipeline processor, simultaneous decoding of multiple specifiers in a variable-length instruction causes a peculiar problem of an intra-instruction read conflict that occurs whenever an instruction includes an autoincrement or an autodecrement specifier which references either directly or indirectly a register specified by a previously occurring specifier for the current instruction. To avoid stalls during the preprocessing of instructions by the instruction unit, register pointers rather than register data are usually passed to the excellent unit because register data is not always available at the time of instruction decoding. If an intra-instruction read conflict exists, however, the operand value specified by the conflicting register specifier is the initial value of the register being incremented or decremented, and this initial value will have been changed by the time that the execution unit executes the instruction.

Abstract: A power manager within a portable laptop computer provides power and clocking control to various units within the computer in order to conserve battery power. Transistor switches controlled by the power manager control the distribution of power and/or clock signals to the various units within the computer. The power manager includes a software routine for continually monitoring the various units and when these units are either not needed and/or not currently in use, power and/or clock signals are removed from a given unit.

Abstract: A personal portable computer system includes peripheral devices such as a printer and a CRT which can be driven by a battery power source. The computer system includes a computer body which contains interface units and power supplied to the interface units is controlled. The interface units are used for supplying power to the peripheral devices.

Abstract: A data processing system provides a desk view which serves as a graphical user interface to the system. The desk view displays detailed miniaturized images of all documents possessed by the user. The compressed document images are user moveable and stackable in the desk view. The desk view also enables user selected operations including mailing, disposing, annotating, stapling, unstapling and printing of documents. User interaction with items of the desk view is communicated through an electronic stylus. Different actions with the stylus provide naturally expected effects. The stylus and desk view provide a simulation of a common office desk and user interaction therewith.

Abstract: A data transfer unit for a small computer system which has a host computer and main and auxiliary storage units, transfers data between the host computer, and the main and auxiliary storage units. The data transfer unit transfers the data, which is outputted from the host computer, from the data buffer to both the main and auxiliary storage units simultaneously, in an operation mode in which data is transferred from the host computer to the storage units. When an error occurs in the main or the auxiliary storage unit, the data transfer unit transfers the correct data from the other storage unit which is operating normally, to a substitute address in the storage unit in which the error has occured.

Abstract: Apparatus for hot removal from/insertion to a connection bus of a non-removable-media magnetic recording unit, comprising a plurality of electromagnetic switches for isolation of the signal terminals of the unit from the bus, thereby preventing noise injection into the bus; control and timing circuits for deenergization of the unit only after opening of the switches and for enabling removal of the unit only after deenergization and circuits for imparting to the signal terminals of the unit a bias voltage intermediate or close to the electrical signal levels present on the bus, the insertion occurring by closing the switches when the unit is already powered and the terminals are biased so as to minimize the amplitude of the noise injected onto the bus.

Abstract: Disclosed is a computer data interface (6) for connecting a handheld computer (4) and a desktop computer (2). The computer data interface includes a cable (8) having connectors (10 and 12) at each end thereof. Mounted in one of the connectors is an adapter circuit for receiving data signals from the handheld computer and transmitting the signals to the desktop computer at a voltage levels compatible with the desktop computer. Similarly, the adapter circuit receives signals from the desktop computer and transmits the signals to the handheld computer at voltage levels compatible with the handheld computer. The adapter circuit is powered by the desktop computer to prevent draining the batteries of the handheld computer.

Abstract: A digital data processing system including a plurality of processors processes a program in parallel to load process data into a two-dimensional matrix having a plurality of matrix entries. So that the processors will not have to synchronize loading of process data into particular locations in the matrix, the matrix has a third dimension defining a plurality of memory locations, with each series of locations along the third dimension being associated with one of the matrix entries. Each processor initially loads preliminary process data into a memory location along the third dimension. After that has been completed, each processor generates process data for an entry of the two-dimensional matrix from the preliminary process data in the locations along the third dimension related thereto.

Abstract: A slave controller formed on a single semiconductor substrate executes a built in control algorithm in response to a command supplied from a master controller. Upon completion of command execution, the controls respond to predetermined information contained within the command by branching internal control operation in accordance with the new command. The controls then suspend a series of operations for executing the new command upon detection of the branch condition. Once the internal state has been changed over, the slave controller sends an instruction to the master controller.

Abstract: A block diagram editor system and method is implemented in a computer workstation that includes a CRT and a mouse, graphics and windowing software, and an external communications interface for test instruments. The computer is programmed for constructing, interconnecting and displaying block diagrams of functional elements on the CRT. From prestored routines for each functional element, the software assembles and executes a program that emulates the functional operations of each element and transfers data from output from each element in turn to an input of a succeeding block, as determined by the block diagram configuration. The block functions include signal generating and analysis functions, and functions for control of various types of test instruments, which can be interactively controlled through the CRT and mouse. The computer converts desired outputs of the instruments into control settings and receives, analyzes and displays data from the instruments. Blocks can also be grouped into macroblocks.

Abstract: A system control unit (SCU), adapted to operating a plurality of central processor units (CPUs) in a parallel fashion in combination with at least one input/output (I/O) unit and for allowing the CPUs and I/O units to controllably access address segments of a system memory, arbitrates communication requests received at the SCU ports from the CPUs and I/O units in such a manner that available system resources are optimally used, while at the same time guaranteeing that all requests are granted within a reasonable period of time. Incoming communication requests are stored, and from there these incoming communication requests are selected, on the basis of a pre-defined prioritizing scheme, commands corresponding to requests that are to be arbitrated. For the command corresponding to each request selected for being arbitrated, there is generated a first vector defining all system resources that are required for executing the command.

Abstract: In computer systems deliberate initializations/resets of the processor latches which represent the internal processor states are necessary to erase only such information which is not required for a subsequent operation, e.g., processing/logging error data, prior to a processor start. One or more reset areas are defined which are initialized/reset in a staggered mode, where in each area a group of latches is assembled which have to be initialized/reset depending on the cause, e.g., power-on, for such a system initialization/reset. The latches within a reset area are connected to form shift registers which are initialized/reset by propagating a binary zero through all latches of the area(s) to be reset.

Abstract: A method for arbitrating access by a plurality of agents to a bus utilizes a priority access list. Each agent in the plurality of agents has a position on the priority access list. This position indicates the agent's relative priority level of access to the bus. When at least one agent from the plurality of agents requests access the bus, bus access is granted to the agent among the requesting agents which is highest on the priority access list. Once an agent from the plurality of agents has gained access to the bus, the agent which gained access to the bus is moved to the bottom of the priority access list.

Abstract: A parallel processor is disclosed which combines the advantages of an array of bit-serial processors and an array of word-oriented processors. Further, the invention provides for ready communication between data organized in bit-serial fashion and that organized in parallel. The processor comprises a plurality of word-oriented processors, at least one transposer associated with each processor, said transposer having n bit-serial inputs and m bit parallel outputs and a bit-serial processor associated with each bit-serial input of the transposer. The parallel processor further comprises a memory for each bit-serial processor and a data bus interconnecting the memory, the bit-serial processors and the bit-serial inputs of the transposer. The transposer converts serial inputs to parallel, word organized outputs which are provided as inputs to the word-oriented processors.

Abstract: When a no-communication state is detected for a predetermined time of time during communication in response to an interrupt designation to or from an apparatus on the other end of the line, an operation of a time monitoring timer for terminating the communication is interrupted. The time monitoring timer is restarted in response to a restart designation. Therefore, communication can be continued without interrupting an interrupt/restart service provided by, e.g., an ISDN due to a time-out error. When a trouble which disables communication occurs during communication, an interrupt service is requested to a network. When the trouble which disables communication is recovered, a restart service can be requested to the network. In this case, communication can be normally restarted without being accidentally terminated intermediately.

Abstract: Arbitration and control circuitry for monitoring the two processors sharing a system bus to insure fair access to system resources and to sense error conditions which occur in order to hold access for the processor involved until the error condition is cleared. The arbitration circuitry provides for two levels of bus access requests where one level involves normal requests and a second level involves priority request which take precedence over normal requests.

Abstract: A procedure, enabled in software, and applied to a cache/disk environment controlled by a host computer operating through a Block Multiplexor Channel Interface and Storage Control Unit, functions to use FIPS 97 and FIPS 60 protocols to execute data transfers between host processors and a plurality of disks whereby simultaneous operations can function with up to 16 disk units. Up to seen I/O requests can be queued on each of the 16 disk units while the system can normally operate in the cache/disk mode. Additionally, the system can operate in the disk-only mode or storethrough mode.

Abstract: A document retrieval system retrieves a registered document from a document database responsive to a designated retrieval condition including one or a plurality of designated keywords. The document retrieval system includes a storage for storing keyword relationships which indicate relationship values of keywords and relations of the keywords and registered documents, an input part for designating a retrieval condition including one or plurality of designated keywords, where the retrieval condition determines a registered document which is to be retrieved from the storage, a selector for selecting a plurality of keyword relationships based on the retrieval condition and for converting the selected keyword relationships into analog signals, an analog operation circuit for calculating a relevance of document based on the analog signals, and a converter for converting the calculated relevance of document into a digital value.