Abstract: An audio signal data processing system comprises input device for sequentially supplying an audio signal data, data memory control device for writing the audio signal data into a data memory and reading-out the data from the data memory, delay memory control device for sequentially reading-out the audio signal data from the data memory and storing the data into a location of a delay memory indicated by a writing address and for reading-out the audio signal data from a location of the delay memory indicated by a reading address and writing the data into the data memory, address designating devices for designating the writing and reading addresses, arithmetic device for multiplying a predetermined coefficient data to the audio signal data having been read-out by the delay memory control device and written into the data memory, and output device for providing the audio signal data in accordance with a result of operation by the arithmetic device.

Abstract: In a computer system equipped with a large number of registers which have an access time much shorter than that of a main memory, a register designating address part in which the assignment of an area register having a register address of a register area as its value and the assignment of a register displacement value expressing a relative register address within the register area are combined is provided in each instruction so that, even when physical registers are increased, save and restore of registers attendant upon task switches, etc. may be lessened to attain a raised speed of program run processing.Besides, an address part for designating the main memory is provided in the same instruction.

Abstract: A computer system for creating and manipulating subprocesses in a dynamic model of information management systems of organizations. The system enables a user to "explode" a process from a graphical representation, or diagram, into its corresponding subprocesses. By performing this process explosion, high-level processes and primitive processes are created. A high-level process is one which has one or more corresponding subprocesses, whereas a primitive process is one which has no corresponding subprocesses. A diagram may then be generated for each primitive process. In addition, the resulting exploded process may simultaneously be displayed with the displayed process from which it is derived. In a similar fashion, subprocesses may be "hidden" within a process, creating high-level processes from groups of primitive processes.

Abstract: The RAM includes sub-arrays having odd and even memory locations, respectively. A data move instruction results in externally generated row and column address signals which are decoded to cause a first memory location, in one of the sub-arrays, to be selected and data to be read. The next memory location in sequence, in the other of the sub-arrays, is then selected, without necessity for an additional set of row address signals, for writing of the read information. The row decoder includes row indexing circuitry actuatable upon receipt of a shift signal signifying that the first memory location is in the last column of a given row. When the shift signal is received, the write location is automatically selected to be in the succeeding row.

Abstract: Preferred embodiments include systems with two processors and an interconnected modem, one processor functioning as a control for both the modem and the second processor. This permits remote communication with the second processor for test or reconfiguration purposes.

Abstract: In a video computer system having a dual-port bit-mapped RAM unit incorporating a shift register, provision is made for coupling data between column lines and the shift register, and for simultaneously preventing any column line from being coupled with the random data output terminal of the RAM unit. Accordingly, this prevents two or more different data bits from appearing simultaneously from the RAM unit and causing confusion as to which is the valid signal and which is a spurious signal.

Abstract: A processor functioning as a coprocessor attached to a central processing complex provides efficient execution of the functions required for database processing: sorting, merging, joining, searching and manipulating fields in a host memory system. The specialized functional units: a memory interface and field extractor/assembler, a Predicate Evaluator, a combined sort/merge/join unit, a hasher, and a microcoded control processor, are all centered around a partitioned Working Store. Each functional unit is pipelined and optimized according to the function it performs, and executes its portion of the query efficiently. All functional units execute simultaneously under the control processor to achieve the desired results. Many different database functions can be performed by chaining simple operations together. The processor can effectively replace the CPU bound portions of complex database operations with functions that run at the maximum memory access rate improving performance on complex queries.

Abstract: An electronic key which includes a pseudo-random number generator. If the correct password is received, the contents of a secure memory will be outputted by the electronic key. However, if an incorrect password is received, that password will be used as a seed value for the pseudo-random number generator, and the resulting value will be outputted.Thus, if a copier exercises the key through all possible passwords, the incorrect passwords, as well as the correct password, will result in the same output data every time it is tried.

Abstract: A storage system for data words in which error correction bits are generated for each data word and are stored independently from the data word on a separate mechanically-driven medium. In another aspect, the storage system serves a wide high throughput parallel bus by storing different portions of each data word that appears on the bus in different asynchronous storage units.

Abstract: A portable computer that is capable of storing one or more application programs and designating one or more program running-start lines by a key input for each application program is provided. The portable computer includes a memory for storing the addresses of the program running-start lines for the previously executed programs, a decision unit for determining whether or not the memory has stored the address of the program running-start line that corresponds to the key input, a first processor for executing the program when the decision unit determines that the address of the program running-start line corresponding to the key input exists in the memory and a second processor for storing the address of the program running-start line corresponding to the key input in the memory when the decision unit determines that the address does not exist in the memory.

Abstract: A pipeline processor adapted for a microprocessor executes pipeline processes. The pipeline processes comprise the steps of reading a machine language instruction; decoding the read instruction; generating an address according to the decoded instruction; reading operand data from a cache memory according to the generated address; executing the instruction; and writing data into the cache memory. When the machine language instruction is a write instruction, the operand data reading step involves a process of searching the cache memory for the address where data is to be written. A result of the search is held in flag memories. Thereafter, the data writing step involves a process of referring to the flag memories, and is completed in one machine cycle.

Abstract: A request is issued in response to an instruction to a memory buffer control unit in accordance with one of first and second specific access methods. The request comprises a request code and a memory address. The first specific access method comprises the steps of holding preliminarily the request code in a register, producing the memory address by using an address syllable included in the instruction, and delivering the memory address and the request code held in the register to the memory buffer control unit.

Abstract: Arbitration logic is provided to receive conflicts between a timekeeping system and a user system which share a common memory. The common memory is comprised of an array of dual memory cells, each of which has a timekeeping cell and a user cell and circuitry for transferring data from the timekeeping cell to the user cell or from the user cell to the timekeeping cell. User data is written into the user cells when it is available and immediately thereafter is transferred from the user cells to the timekeeping cells. Data from the timekeeping system is inhibited from being written into the timekeeping cells if, during the present update cycle of the timekeeping system, the user writes data into the common memory.

Abstract: A computer system for establishing an adaptive window system within a dynamic model of information systems of organization. The system includes a plurality of editors which enable a user to interact with the system. The window system includes predetermined criteria against which design data of one or more of the editors is compared. An options window then displays those options which meet the criteria, generally corresponding to syntactically permissible options, at any time during the model building process.

Abstract: An activity monitor for monitoring activity on a bus connecting a plurality of processors, monitors the bus to determine the bus master and other bus activities. In response thereto, predetermined memory locations are enabled to count events on the bus or calculate time spans for various bus activities.

Abstract: A data shuffler of the pipeline type receives successive trains of n sequential data words and rearranges data words in each train according to a predetermined order. It comprises p (p.ltoreq.n) elementary processing units arranged in series. Each unit comprises an input, an output, a one-word storage register (20), a steering means (21) in order, in response to a binary control, to connect the input to the output either directly or through the register; and means for periodically supplying to each of the p steering means a sequence of n control bits determined as a function of said predetermined order.

Abstract: A parallel processing system including a virtual processing instruction and address generator, for generating processor cell instructions to a parallel processing array such as a multi-dimensional processor array which may have fewer processor cells than the number of nodes in the problem space. The system partitions the memory of each physical processor cell into several equal sections, each section being associated with one node of the problem space. The instruction generator then produces a sequence of processor cell instructions for each node of the given problem space, with appropriate address modifications for each sequence of instructions provided by an address relocation circuit.

Abstract: A link sorted memory and method of storing and sorting data that provides for rapid sorting and retrieval of data stored in an unsorted fashion. The link sorted memory comprises a data memory for storing unsorted data, and a linking memory that functions as a pointer table to related memory addresses in the data memory. A sorting coprocessor is provided that stores the data unsorted in the data memory, scans the data words for a sort attribute, and uses the sort attribute to create the pointer table that links the unsorted stored data words. Sorting and retrieval of the unsorted data in the data memory is achieved by incrementing a counter, for example, that steps through the addresses stored in the linking memory to sequentially retrieve all data words having the sort parameter.

Abstract: A fast interrupt mechanism is capable of simultaneously interrupting a community of associated processors in a multiprocessor system. The fast interrupt mechanism enables the more effective debugging of software executing on a multiprocessor system by allowing all of the processors in a community associated with a parallel process to be halted within a limited number of clock cycles following a hardware exception or processor breakpoint. The fast interrupt mechanism consists of a set of registers that are used to identify associations among multiple processors, a comparison matrix that is used to select processors to be interrupted, a network of interconnections that transmit interrupt events to and from the processors, and elements in the processors that create and respond to fast interrupt events.

Abstract: An image processing system having operating and stand-by modes of operation which are to be selectively put into effect, including a plurality of slave data processors each operative to execute a set of predetermined functions assigned thereto, a master data processor for controlling the operation of each data processor, the master data processor being operative to output a data processing command requesting any of the slave data processors to execute any of the predetermined functions assigned to the slave data processor and a control command predominant over the communication of data dictating the operation of each slave data processor, and an interface bus providing connection between the master data processor and each slave data processor for allowing transmission therethrough of the data processing command and the control command to any of the slave data processors, the master data processor being operative to detect a state in which the master data processor is currently coupled to any one of the slave