Abstract: A bi-directional bus adapter coupling a system bus, which operates at a first speed using a first protocol, and an IO bus, which operates at a second speed using a second protocol, and allowing data transfering devices on either bus to transfer data to or from devices on the other bus. The bus adapter includes a cycle generation mechanism which is responsive to data cycles from one of the buses in order to generate bus cycles needed to complete a data transfer to a device on the other bus. The bus adapter includes a synchronization mechanism for converting the plurality of data cycles generated by the cycle generation mechanism from either the first speed to the second speed or vice versa. The bus adapter includes bi-directional data path mechanism for routing data between the system and IO buses according to said protocols, such that the data path directs bytes of data to specific data lines to perform byte steering and dynamic bus sizing on the data from the system bus to the IO bus.

Abstract: An instruction caching system comprises meta-instructions which are contained within the program being executed. A meta-machine, which is a small segment of software, executes the meta-instructions and passes control to the processor itself at appropriate times to execute blocks of instructions from the instruction cache.

Abstract: A method for reducing interrupt processing overhead is applied in situations when it is not necessary to preserve processor state information. A flag is provided to indicate whether or not the processor is available. Upon recognition of an interrupt, an interrupt vector address is computed based, in part, on the state of the processor available flag. If the processor is available, indicating that it is not currently working on a task, there is no need to preserve the processor state information, and the state-saving portions of the interrupt processing routines are bypassed. On the other hand, if the processor is not available, indicating that the it is engaged in a task, the state information must be preserved so that the processor can return to the task after the interrupt is processed. In this case, the state-saving portions of the interrupt processing routines are not bypassed.

Abstract: A computing system including a host processor and at least one intelligent subsystem having attached devices, has two interrupt ports. The one intelligent subsystem and the attached devices are each viewed as a logical device by the host processor, and each is assigned a device identification number. The host processor provides direct and indirect commands to the logical devices. For direct commands, first physical interrupts are provided to the host processor serially from the logical devices through an Interrupt Status Port. For indirect commands, logical interrupts are stored in predetermined bit positions in a Device Interrupt Indentifier Port (DIIP) in accordance with the device identification numbers. A second single physical interrupt is provided to the host processor as long as there is at least one logical interrupt pending from at least one logical device as the result of an indirect command.

Abstract: The reliability of a tamper resistant module for safeguarding stored information, e.g. in an electronic computer system, is improved to deny access to the system by an unauthorized person or at least to a specific portion of the system. For this purpose, the module has for example a pair of substrates which are bonded together to confine confidential data inside the module. On the outer surfaces of the substrates, a plurality of logical elements, such as transistors, form detecting memory devices. The plurality of these detecting memory devices are operative under a normal condition, but at least one of these detecting memory devices is rendered inoperative when a tampering is applied to the outer surface of the substrate. In a tamper free normal situation all memory devices work properly. The inoperability of any of the detecting memory devices is detected when tampering occurs. When the tamper is detected, the confidential data confined within the module are erased.

Abstract: A scbok line is connected to a register file and other units, such as an execution unit and a multiply/divide unit, in a data processing system. A mem scbok line is connected to the register file and other units, such as an instruction unit and a memory interface unit. Each unit connected to the scbok line can pull the line to indicate that it is busy. Each unit connected to the mem scbok line can pull the line to indicate that it is busy. The scbok line indicates, when asserted, that a unit or a register in the register file that is busy with a previous instruction is not available to an instruction for a register file operation. The mem scbok line indicates, when asserted, that a unit or a register in the register file that is busy with a previous instruction is not available to an instruction for a memory operation. Registers are checked concurrently with the issuing of an instruction.

Abstract: Monitoring system for an electronic digital system. It includes an electronic digital control unit, a plurality of peripheral units, a bus system, the various system parts, and further an output circuit connected to the control unit. It further includes an output stage circuit with inputs connected to the output circuit, and outputs transmitting signals to the peripheral units for interrogating fault conditions therein, an interrupt trigger circuit with outputs connected to the control unit, and a digital filter connected between the monitoring system and the peripheral units for filtering out noise signals from the peripheral units.

Abstract: Updated images of messages are passed between asynchronous digital processors using dual port shared memory. In the basic form of the invention, three buffers in shared memory are assigned to each message. Where one of the processors is a controller for a data link channel carrying n messages, 2n+1 buffers are provided in free shared memory space with 2 buffers assigned to each message at all times and a common buffer serving as the third buffer for all of the messages. Where linked buffers in local memory of a controller processor receive message updates from a data highway, two buffers in shared memory are assigned to each message and a linked buffer in the controller local memory serves as the third buffer. The buffers containing the message updates are passed between processors by use of a buffer status array in shared memory. A semaphore lock in the array permits only one processor at a time to assign or release buffers.

Abstract: In a debugging microprocessor having a function of elongating a bus cycle in response to an external ready signal and used in a microprocessor development support system having a function capable of tracing and analyzing the result of execution, there is provided a generator for generating a bus cycle end signal for the microprocessor development support system. The generator comprises a ready detection circuit receiving an external ready signal, a clock signal and an enable signal which is rendered active only when the debugging microprocessor is in a condition capable of accepting data. The ready detection circuit operates to detect the status of the external ready signal at a time defined by a clock appearing when the enable signal is active, so as to generate an internal ready signal if the external ready signal is active.

Abstract: A slot determination mechanism wherein a number of bus units establish their positions along the bus and the total number of units on the bus. The units are connected in a bidirectional daisy chain. A one-cycle reset pulse is sent downstream to unit 1 (the upstream unit). Each unit on receiving one or more pulses from upstream sends that many plus one pulses downstream and then sends a one pulse upstream. Each unit then transmits upstream whatever it receives from downstream. The number of pulses received from upstream provide the slot number. The total number of pulses received from upstream and downstream provide the total number of units.

Abstract: A cache controller is coupled to a cache memory coupled through a bus to a microprocessor, for controlling the cache memory in response to a signal from the microprocessor. The cache controller comprises an address signal terminal and a control signal terminal for receiving an address signal and a control signal from the microprocessor, and a clamp signal terminal for receiving a clamp signal from the microprocessor. The cache controller also includes an input circuit coupled to the address signal terminal, the control signal terminal and the clamp signal terminal for outputting the address signal and the control signal as they are when the clamp signal is inactive and for generating an output address signal and an ouput control signal having a predetermined logic level when the clamp signal is active.

Abstract: In this computer system, a plurality of processing elements (PE), each having at least two channel processors which manage corresponding communication channels separately, are connected in a ring via the channel processors to form a processing element loop (10). Some of the processing elements are designated as process managers (SM.sub.1 -SM.sub.n) which manage the corresponding process frame groups (20) comprising a predetermined number of process frames. At least one other element is designated as a master manager (MM) which manages those process managers. The respective process managers (SM.sub.1 -SM.sub.n) each allocate a predetermined process to any one process frame of the process frame group (20) which that process manager manages in accordance with each requirement from the master manager (MM) to cause that process frame to execute the predetermined process.

Abstract: A data processing device wherein messages are inputted for a plurality of recipients. The recipients' names are displayed along with the number of messages. When a message is inputted for a new recipient, the recipient's name as well as the message are automatically stored. In the event the recipient's name has already been stored only the message is stored.

Abstract: A computer-aided design method for restructuring computational networks to minimize latency and shim delay, suitable for use by a silicon compiler. Data-flow graphs for computational networks which use trees of operators, each performing associative and commutative combining of its respective imput operands to generate a respective output operand, are converted to data-flow graphs with multiple-input operators. Data-flow graphs with multiple-input operators, after being optimally scheduled, are converted to data-flow graphs which use trees of dual-input operators or of dual-input and three-input operators, those trees having minimum latency and shim delay associated with them. These data-flow graphs then have shim delay minimized in them, e.g. by being subjected to linear programming.

Abstract: A system and method in which client access to data at a server is synchronized to keep the data consistent by ensuring that each portion of the data accessible for modification at a node is not accessible for reading or modification by any other node, while allowing portions of the data accessible only for reading to be accessible by any number of nodes. If a conflicting request arises from a different client the server must revoke data that has been previously distributed to a client. For a revoke.sub.-- bytes request, all outstanding get.sub.-- bytes are marked so that the bytes that are being requested to be revoked will be discarded when they do arrive at the client. To insure that read and write system calls on a file are performed in a serializable fashion throughout a distributed environment, each machine at which a read is being performed must acquire a read token and each machine at which a write is being performed must acquire a read/write token from the server for the file.

Abstract: A system for displaying "help" information concerning the functioning of the controls of an electronic system. A "help" control is provided which, when operated, places the system in a "help" mode. When the system is in the "help" mode, system controls are disabled from performing their normal function and, in response to the operation of a control and were appropriate to an indication of the current state of the system, a selected "help" text is displayed. The system is adapted to operate for both analog and digital controls and to provide the "help" text in a window on the display so that normal operation of the system may continue while the "help" text is being displayed.

Abstract: To create a snapshot copy of selected elements of a database in a data processing system, the selected elements are copied sequentially to a secondary storage device. During the copying operation, when a task requests to delete one of the selected elements from the database before it is copied to the secondary storage device, a record is made to identify the requested element, the task is allowed to continue processing. After the element has been copied to the secondary storage device, the identified element will be deleted based upon the record. Also, during the creation of the copy, when a task requests to update one of the selected elements, a duplicate copy of the requested element is created and the task is allowed to update the requested element. When it is time to copy the requested element to the secondary storage device, the duplicate copy will be used.

Abstract: A system which includes a microprocessor (or microcontroller) and an auxiliary chip which monitors the system power supply voltage and performs related functions for the microprocessor, and also provides a watchdog function to monitor the microprocessor's activity. The auxiliary chip itself can put to sleep by the microprocessor to minimize power consumption. The sleep mode of the auxiliary chip saves power by shutting down many of the input-sensing circuits, and the watchdog function. The sleep command is not accepted unless it stands in the proper timing relationship to a signal on the strobe pin. This permits the power savings of the sleep mode to be realized, without any risk of the system being placed in the sleep mode due to an out-of-control system condition.

Abstract: Change processing of a replica database is accomplished by separating redo records obtained from the transaction log of a primary database into respective queues. The redo records are separated such that all transaction records for a unit of transfer (page) of the primary database are placed on the same queue in log sequence. Each queue is linked exclusively to one of a plurality of parallel queue servers. Each queue server applies to the replica database the redo records in the queues which it exclusively serves. The replica database is thereby made consistent with the primary data by a lock-free updating mechanism which services the pages of the replica database in parallel.

Abstract: A Command interface includes ports for transferring information between a host processor and at least one intelligent subsystem which may have attached devices. A Command Interface port receives either a direct command or an indirect command from the host processor, which commands are indicative of a type of operation to be performed by the one subsystem or an attached device. An Attention port receives a code from the host processor which is indicative of which one of the direct command or the indirect command is received at the Command Interface port, and which is also indicative of which of the one intelligent subsystem or a device is to execute the command. A command busy/status port receives a code from the one intelligent subsystem which is indicative of whether or not the Command Interface port and the Attention port are busy, and whether or not the one intelligent subsystem is accepting or rejecting commands. The host processor can read this port without altering or updating the code.