Abstract: A method for determining a patterning device pattern. The method includes obtaining (i) an initial patterning device pattern having at least one feature, and (ii) a desired feature size of the at least one feature, obtaining, based on a patterning process model, the initial patterning device pattern and a target pattern for a substrate, a difference value between a predicted pattern of the substrate image by the initial patterning device and the target pattern for the substrate, determining a penalty value related the manufacturability of the at least one feature, wherein the penalty value varies as a function of the size of the at least one feature, and determining the patterning device pattern based on the initial patterning device pattern and the desired feature size such that a sum of the difference value and the penalty value is reduced.

Abstract: Disclosed is a method (310) for providing operational feedback during power transfer in a wireless power transfer system. The wireless power transfer system comprises a power transmit device arranged to transfer power over an inductive wireless power transfer interface operating at a transmit frequency to a power receive device. The wireless power transfer system is adapted to transfer information at half duplex using Frequency Shift Keying, FSK, in one direction and Amplitude Shift Keying, ASK, in the other direction. The method comprises transferring (308), at the transmit frequency by the power transmit device, power to the power receive device. During the transferring (308), the method further comprises transmitting (311), at the transmit frequency by one of the power transmit device or the power receive device, a first data packet to the other of the power transmit device or the power receive device using one of two modulation types being FSK or ASK.

Abstract: A charging device for connecting an electrical energy store of a motor vehicle to a charging station for electrical energy includes a charging cable having at least one line for conducting a charging current and at least one connection element via which the charging cable is connectable to a corresponding connection element between the energy store and the charging station. At least one latent heat store is provided on the charging cable and/or on the at least one connection element and can be used to absorb heat generated during the charging process.

Abstract: A management server including a server performing maintenance and management to a plurality of storage battery apparatuses included in an object of charge and discharge control by a control server. The management server includes processor. The processor is configured to execute a specification process, a selection process, a notification process. The specification process includes a process of specifying each of deterioration degree of the plurality of the storage battery apparatuses. The selection process includes a process of selecting an excluded storage battery apparatus excluding from the object of the charge and discharge control by the control server, out of the plurality of the storage battery apparatuses, based on the deterioration degree specified by the specification process. The notification process includes a process of notifying, to the control server, notification that the charge and discharge control to the excluded storage battery apparatus selected by the selection process is unable.

Abstract: A method of modeling a nonlinear component includes providing a physical model for modeling a characteristic of the nonlinear component defined by a physical expression having a physical nonlinear function depending on variables and parameters of the nonlinear component; determining performance data for the characteristic; extracting global parameter values for the parameters based on the performance data; extracting local parameter values for the selected parameter, while keeping fixed the extracted global parameter values for the remaining parameters, based on the performance data corresponding to the characteristic using the physical expression; training an ANN function from the extracted local parameter values for the selected parameter depending on a variable; and determining a hybrid model for modeling the characteristic of the nonlinear component defined by a modified physical expression including the physical nonlinear function, the remaining parameters, and the trained ANN function depending on the v

Abstract: Circuit devices include a first chip that includes functional blocks. A second chip has routing circuitry that provides configurable signal communications between functional blocks of the first chip and configuration memory that controls the routing circuitry and that further controls operation of the functional blocks of the first chip.

Abstract: The energy storage apparatus includes an energy storage device, a circuit breaker connected in series with the energy storage device, a reception unit that receives a discharge instruction to discharge remaining electric power of the energy storage device, and a management unit. The management unit executes protection processing of opening, when a state of charge of the energy storage device drops below a predetermined threshold value, the circuit breaker to protect the energy storage device from overdischarging, and protection release processing of releasing protection of the energy storage device when the discharge instruction is received by the reception unit.

Abstract: A contactless electricity supply system for a vehicle includes a power transmitter coil unit provided on a ground-side and a lifting device for lifting up the power transmitter coil unit from the ground. The power transmitter coil unit supplies electricity to a power receiving coil unit by magnetic coupling therewith. The power transmitter coil unit includes a case that houses a power transmitter coil. A bulge is formed on an upper face of the case around a winding center axis of the power transmitter coil wounded in a planar manner in a plan view.

Abstract: The present invention relates to a quantum computing unit comprising a superconducting substrate or other superconducting component, at least three outer Majorana modes, and at least one inner Majorana mode, wherein the at least three outer Majorana modes are located along an outer perimeter, and wherein the at least one inner Majorana mode is located within the outer perimeter. This spatial configuration of the four participating Majorana modes allows to control the time-dependent coupling between the respective Majorana modes. The related quantum gates can be performed perfectly in a finite time, preferably with a frequency of up to several GHz. These include the braiding gate, the ?/8 magic phase gate, the ?/12 phase gate, and, for multi-qubit systems, the CNOT gate. The robustness of the mechanism guarantees that for special times the quantum gate is conducted the quantum gate is perfectly realized. This property is independent of material specific parameters.

Abstract: Methods and systems for performing timing analysis during the design of a circuit are described. In one embodiment, a simulation system can generate an effective resistance value (or an impedance value based on the effective resistance value) for an instance and use the effective resistance value in a simulation to determine a minimum timing delay for the instance when only the instance switches during such simulations.

Abstract: A computer-implemented method includes receiving, by a processor, a physical design block and a physical hierarchy of a chip design of a chip. Further, the method includes extracting, by the processor, one or more features of a macro to be added to the chip design based on a logic synthesis of the chip design. Further, the method includes predicting, by the processor, specifications of the macro to be added to the chip design based on the physical design block, the predicting performed using a pre-trained machine learning model. Further, the method includes using, by the processor, the specifications of the macro to perform a physical synthesis of the chip design to determine a physical layout of the chip.

Abstract: Provided are a chip and a pin line-out design method therefor, which are applied to a BGA packaged chip. The method includes: according to pin position information and pin definition information of a chip, determining a number of circuit board layers required for pin line-out of the chip (S1); allocating line-out layers to pins of the chip in their respective circuit boards (S2); and according to a pin density and transmission line width requirement of the chip, determining a specification of a via hole in each circuit board for leading the pin of the chip out to the corresponding line-out layer, to perform a corresponding line-out design on the basis of the via hole (S3). It may be seen that the described unified pin line-out design for the BGA packaged chip is more refined, and the quality of the line-out design of the pins of the chip is ensured.

Abstract: Systems, methods, and devices are described herein for integrated circuit (IC) layout validation. A plurality of IC patterns are collected which include a first set of patterns capable of being manufactured and a second set of patterns incapable of being manufactured. A machine learning model is trained using the plurality of IC patterns. The machine learning model generates a prediction model for validating IC layouts. The prediction model receives data including a set of test patterns comprising scanning electron microscope (SEM) images of IC patterns. Design violations associated with an IC layout are determined based on the SEM images and the plurality of IC patterns. A summary of the design violations is provided for further characterization of the IC layout.

Abstract: A method for determining a deformation of a resist in a patterning process. The method involves obtaining a resist deformation model of a resist having a pattern, the resist deformation model configured to simulate a fluid flow of the resist due to capillary forces acting on a contour of at least one feature of the pattern; and determining, via the resist deformation model, a deformation of a resist pattern to be developed based on an input pattern to the resist deformation model.

Abstract: In some aspects, a mask pattern is accessed. The mask pattern is for use in a lithography process that prints a pattern on a wafer. The mask pattern is applied as input to a deterministic model of the lithography process to predict a characteristic of the printed pattern. The deterministic model is deterministic, but it accounts for local stochastic variations of the characteristic in the printed pattern.

Abstract: Systems, methods, and computer programs products are described for optimizing circuit synthesis for implementation on an integrated circuit. A register transfer level code description of logic behavior of a circuit. The register transfer level code description is converted into structurally defined circuit designs for multiple types of components and feature size technologies. A floor plan of each structurally defined circuit design is generated. A physically simulated circuit is created for each floor plan. A range of operating conditions is swept over to analyze power, performance, and area of each physically simulated circuit.

Abstract: Disclosed is an operating method of an electronic device which includes receiving a design layout for manufacturing the semiconductor device, generating a first layout by performing machine learning-based process proximity correction (PPC), generating a second layout by performing optical proximity correction (OPC), and outputting the second layout for a semiconductor process. The generating of the first layout includes generating a first after cleaning inspection (ACI) layout by executing a machine learning-based process proximity correction module on the design layout, generating a second after cleaning inspection layout by adjusting the design layout based on a difference of the first after cleaning inspection layout and the design layout and executing the process proximity correction module on the adjusted layout, and outputting the adjusted layout as the first layout, when a difference between the second after cleaning inspection layout and the design layout is smaller than or equal to a threshold value.

Abstract: An aspect of the disclosed embodiments is a method for printed circuit board (PCB) component placement comprising: graphically displaying, on a display device, PCB design features of a PCB design; and providing a user interface control for designating one or more of the PCB design features as electrical contacts for a first selected electrical component. Other aspects are disclosed.

Abstract: The present disclosure relates to a smart battery. The smart battery includes a battery shell, layered cells, a positive electrode, a negative electrode, an embedded multi-source sensor group and an intelligent chip. The smart battery can detect the temperature and the pressure of the core of the battery and the current of the battery in real time by using the intelligent chip and the embedded multi-source sensor group, thereby realizing a real-time monitoring of the working state and safety state of the battery, and improving a safety and the reliability of the battery on the basis of realizing the self-sensing function of the battery. The modification to the conventional battery structure by adding the intelligent chip and the embedded multi-source sensor group makes up the gap in research and development, manufacturing and production of the smart battery on the premise of ensuring that the battery volume remains unchanged.

Abstract: Systems, computer-implemented methods, and computer program products to facilitate entity steering of a running quantum program are provided. According to an embodiment, a system can comprise a processor that executes computer executable components stored in memory. The computer executable components can comprise a steering component that adjusts at least one parameter corresponding to a running quantum program to define at least one modified parameter. The computer executable components can further comprise an execution component that executes one or more shots of the running quantum program based on the at least one modified parameter.