Abstract: A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.

Abstract: A portable information handling system glass ceramic housing integrates plural wireless charging coils on one side and plural coil interface traces on an opposing side that interface with conductive material disposed in through glass via openings. Conductive contacts interfaced with the coil interface traces and exposed at the glass ceramic housing interior couple to a printed circuit board assembly through pogo pins that bias against the conductive contacts to communicate power from the wireless charging coils to the charger of the information handling system. The conductive contacts co-locate with a logo etched into the glass ceramic housing to provide an aesthetically pleasing wireless charging solution.

Abstract: Embodiments described herein relate to a system, software, and a method of using the system to edit a design to be printed by a lithography system. The system and methods utilize a server of a maskless lithography device. The server includes a memory. The memory includes a virtual mask file. The virtual mask file includes cells and the cells include sub-cells that form one or more polygons. The server further includes a controller coupled to the memory. The controller is configured to receive a replacement table. The replacement table includes instructions to replace the cells of the virtual mask file. The controller is further configured to replace the cells with replacement cells according to the replacement table to create an edited virtual mask file.

Abstract: A tool for executing performance-aware topology synthesis of a network, such as a network-on-chip (NoC). The tool is provided with network information. The tool uses the network information to automatically stabilizes data width and clock speed for each element in the network that meet the network's constraints and performance requirements. The tool is able to provide the performance-aware topology synthesis rapidly, while honoring the objectives and the network's constraints.

Abstract: A partitioning method for partitioning a group of power-ground (PG) cells is disclosed. The method includes: placing at least one out-boundary PG cell on a substrate, wherein power strips of the at least one out-boundary PG cell are aligned with corresponding power rails on the substrate; and placing at least one in-boundary PG cell on the substrate, wherein power strips of the at least one in-boundary PG cell are aligned with corresponding power rails on the substrate.

Abstract: A computer-implemented method for improved determination of state of health (SoH) of a battery of a device can include determining that the device is in a charging state such that a charge of the battery is increased over a charge procedure; determining that a state of charge (SoC) metric of the battery reported by a battery gauge system has increased by a fixed SoC interval; determining a charge time interval over which the SoC metric of the battery has increased by the fixed SoC interval; and determining a SoH metric indicative of the SoH of the battery based at least in part on the charge time interval; wherein determining the SoH metric is based at least in part on a known relationship between a reference time interval representative of time required to increase a reference battery at full SoH by the fixed SoC interval and the charge time interval.

Abstract: A semiconductor unit is arranged between a motor and an inverter circuit that controls the motor. The semiconductor unit includes a transistor and a controller. The transistor is arranged between the inverter circuit and a positive electrode of a battery that supplies power to the inverter circuit, and controls supplying of power from the battery to the inverter circuit. The controller is connected to a control terminal of the transistor, and controls a control voltage that is a voltage applied to the control terminal. When power starts to be supplied from the battery to the inverter circuit, the controller controls the control voltage to intermittently operate the transistor and also decreases the control voltage, which is applied to the control terminal of the transistor, to be lower than the control voltage at which the transistor is fully activated.

Abstract: A method includes generating a plurality of input vectors based on input signals to an electric circuit, selecting a subset of the plurality of input vectors, and determining a plurality of datapoints based on the selected subset of the plurality of input vectors. Each datapoint of the plurality of datapoints indicates a power consumption of the electric circuit corresponding to an input vector of the selected subset of the input vectors. The method also includes generating, by a processor, a plurality of vector sequences based on the selected subset of the plurality of input vectors. Each vector sequence of the plurality of vector sequences includes a portion of the selected subset of the plurality of input vectors arranged chronologically. The method further includes training a machine learning model based on a first subset of the plurality of vector sequences and a corresponding first subset of the plurality of datapoints.

Abstract: A method of manufacturing an integrated circuit (IC) includes forming a first active region in a first cell. The method includes forming a plurality of second active regions in a second cell, wherein the second cell abuts the first cell. The method includes forming a third active region in a third cell, wherein the second cell is between the first cell and the third cell, and a height of the second cell is different from a height of the first cell or the third cell. The method includes forming a plurality of gate structures extending across each of the first active region, the plurality of second active regions, and the third active region. The method includes removing a first portion of a first gate structure at an interface between the first cell and the second cell between the first active region and the plurality of second active regions.

Abstract: A computer implemented method for designing electrical circuitry is disclosed which comprises: (a) determining types and number of parameters to be optimized and their respective upper boundaries (UB) and lower boundaries (LB) in binary and/or decimal formats for such electrical circuitry using a CAD/CAE/EDA module of a quantum emulator computer; and (b) optimizing the parameters in qubit formats using a quantum evolution optimization module constrained by the upper and lower boundaries; the quantum emulator computer includes the CAD/CAE/EDA program and the quantum evolution optimization module.

Abstract: A system includes a first instance and a second instance of an integrated circuit. The integrated circuits include respective external interfaces with a physical pin layout having transmit and receive pins for a particular bus located in complementary positions relative to an axis of symmetry. The external interfaces of the first and second instances of the integrated circuit are positioned such that the transmit and receive pins for the given I/O signal on the first instance are aligned, respectively, with the receive and transmit pins for the given I/O signal on the second instance.

Abstract: A logic block can be relocated without recompilation from a first area to a second area on a field-programmable gate array (FPGA) if the pattern of fabric tiles in the second area is the same as the pattern of fabric tiles in the first area, and if the two areas have the same dimensions. The design system runs synthesis, placement, and routing on a partition of a design at a first location, exports that partition to a persistent on-disk database, imports one or multiple copies of the partition into a larger design, and moves one or more of the copies from the first area to a target area in the larger design. The compatibility of the second area may be identified based on fabric tile signatures of the first area and the second area.

Abstract: A method and a system for ship stability prediction by weighted fusion of RBFNN and random forest based on GD are provided. Firstly, input characteristics when predicting failure probabilities under different failure modes are determined through prior knowledge. Secondly, a mean square error of k-fold cross-validation is used as performance evaluation criterion of the RBFNN and the RF to search for model capacities of the RBFNN and the RF. Then, network parameters of the RBFNN are updated. Multiple random sample sets are generated using a bootstrap sampling method and are parallelly trained to generate multiple regression trees. A Gini index is used as an attribute division index, and a prediction result of the random forest is obtained. Finally, weight coefficients are introduced for weighted fusion of prediction results of the RBFNN and the RF. The weight coefficient is obtained by solving through iterative optimization of the gradient descent.

Abstract: A method includes instantiating a first plurality of rows in a first region of a fabric. The first region has a height corresponding to a sum of heights of the first plurality of rows. The method also includes instantiating a second plurality of rows in a second region of the fabric. The second region is horizontally adjacent to the first region in the fabric. The second region has a height corresponding to a sum of heights of the second plurality of rows. The method further includes determining whether a row of the first plurality of rows is misaligned with a row of the second plurality of rows and adding a transition region between the row of the first plurality of rows and the row of the second plurality of rows in response.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip floorplan. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip floorplan, comprising placing a respective node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the node to be placed at the time step to a position from the plurality of positions using the score distribution.

Abstract: A layout correction method is provided. The layout correction method includes: providing an initial layout; expanding the initial layout to obtain an expanded layout; correcting the expanded layout to obtain a corrected layout; and obtaining a target layout based on the corrected layout.

Abstract: An integrated circuit (IC) includes a first, second and third semiconductor cell regions. The first cell region includes a first active region having a first dopant type. The second semiconductor cell region abuts the first cell region in a second direction, and includes second and third active regions having correspondingly a second dopant type and the first dopant type. The second active region is between the first and third active regions. The third cell region abuts the second cell region in the second direction, and includes a fourth active region having the second dopant type. The third active region is between the fourth active region and the second active region. The second semiconductor cell region has a height 2H, and the first, second and third semiconductor cell regions collectively have a height 3H.

Abstract: A system determines physical design information along a logic hierarchy of a circuit design. The system accesses physical design metrics associated with different parts of a physical design of a circuit. The system accesses a logic design of the circuit comprising a hierarchy of logic blocks. The system determines the physical design metrics associated with one or more logic blocks of the hierarchy of the logic design based on a relation between the physical design and the logic design. The system configures a user interface to display the hierarchy of the logic design of the circuit along with the physical design metrics associated with the one or more logic blocks of the hierarchy. The system sends the configured user interface for display.

Abstract: Generation of a full register-transfer level (RTL) description of an electronics system includes generating an optimized pipeline configuration from inputs including a database of RTL elements, and a list of configurable pipeline components; and generating the full RTL description with the pipeline components configured according to the optimized pipeline configuration. Generating the configuration includes performing a search for a configuration that optimizes area and timing.

Abstract: A method for detecting whether a battery management system is abnormal includes: calculating a value of a theoretical time constant corresponding to a first cell; determining a preset range of the theoretical time constant; controlling a first switch to turn off for a first time period, turn on for a second time period, turn off for a third time period; measuring a voltage on a first capacitor at end of first time period, to produce a measured voltage of first cell; measuring voltages on first capacitor at least at one time point in third time period, to produce measured capacitance voltages; determining a value of a measured time constant according to at least one of measured capacitance voltages and the measured voltage of first cell; and determining the battery management system is abnormal, if the value of the measured time constant exceeds the preset range of the theoretical time constant.