Abstract: Disclosed herein is a framework to generate ULP, energy-minimal coarse-grain reconfigurable arrays that execute in a spatial vector-dataflow fashion, mapping a dataflow graph spatially across a fabric of processing elements, applying the same DFG to many input data values, and routing intermediate values directly from producers to consumers. The spatial vector-dataflow minimizes instruction and data-movement energy and also eliminates unnecessary a switching activity because operations do not share execution hardware.

Abstract: A field-programmable gate array (FPGA) routing tool within a computer-aided design system. The tool includes an input device for receiving a netlist containing nets with source nodes, sink nodes, and intermediate nodes at fixed positions. The tool further includes a processing circuitry configured with a design router responsible for constructing non-overlapping routing trees for all nets, ensuring connections from source nodes to sink nodes without exceeding fixed routing resource capacity of the FPGA. The design router utilizes incremental routing, which applies deterministic parallel routing to a window of initial iterations with high routing workload and sequential routing to subsequent iterations. Additionally, a display device is provided to continuously exhibit interconnections and routing utilization during the determination of routing trees.

Abstract: Generated instruction sequences captured from software interactions may be executed as part of formal verification of a design under test. Software-instructed commands to be performed to configure a design under test formatted according to an interface implemented by the design under test can be obtained. A sequence to perform the software-instructed commands may be generated to configure the design under test in a hardware design and verification language. The sequence may then be executed to perform the software-instructed commands to configure the design under test and then perform formal verification on the configured design under test.

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a first conductive pattern disposed within a first region from a top view perspective and extending along a first direction, a first phase shift circuit disposed within the first region, a first transmission circuit disposed within a second region from the top view perspective, and a first gate conductor extending from the first region to the second region along a second direction perpendicular to the first direction. The first phase shift circuit and the first transmission circuit are electrically connected with the first conductive pattern through the first gate conductor.

Abstract: A method of manufacturing a semiconductor device includes forming M_1st segments in a first metallization layer including: forming first and second M_1st segments for which corresponding long axes extend in a first direction and are substantially collinear, the first and second M_1st segments being free from another instance of M_1st segment being between the first and second M_1st segments; and (A) where the first and second M_1st segments are designated for corresponding voltage values having a difference equal to or less than a reference value, separating the first and second M_1st segments by a first gap; or (B) where the first and second M_1st segments are designated for corresponding voltage values having a difference greater than the reference value, separating the first and second M_1st segments by a second gap, a second size of the second gap being greater than a first size of the first gap.

Abstract: According to some embodiments, re-programmable and/or reconfigurable analog circuitry may be provided. An image interpreter (e.g., a Micro Control Unit (“MCU”)) may be configured to receive and store an image, generated for a particular application, to facilitate variation trimming of the re-programmable and/or reconfigurable analog circuitry. The variation trimming may, for example, be performed during production of the re-programmable and/or reconfigurable analog circuitry or post-production of circuitry, in the field, after the circuitry is provided to a customer.

Abstract: A semiconductor device includes a first cell. The first cell includes a first functional feature, a first sensitivity region, at least one anchor node, wherein each of the at least one anchor node is different from the first functional feature, and a number of anchor nodes of the at least one anchor node linked to the first functional feature is based on a position of the first functional feature relative to the first sensitivity region. The semiconductor device further includes a second cell abutting the first cell. The second cell includes a second functional feature, wherein the second functional feature satisfies a minimum spacing requirement with respect to the first functional feature.

Abstract: An aspect of the disclosed embodiments is a method for printed circuit board (PCB) component placement comprising: graphically displaying, on a display device, PCB design features of a PCB design; and providing a user interface control for designating one or more of the PCB design features as electrical contacts for a first selected electrical component. Other aspects are disclosed.

Abstract: A method for correcting a mask patter includes: acquiring an initial pattern of a mask, the initial pattern including a scribe line area and die areas which are spaced, and the scribe line area is located between two adjacent die areas, each of the die areas includes at least one die sub-area and at least one first sub-test element group (TEG) area, and the scribe line area includes scribe line sub-areas and second sub-TEG areas, the first sub-TEG area and the second sub-TEG area are adjacent to each other, and the first sub-TEG area and the second sub-TEG area constitute a TEG area; performing an optical proximity correction (OPC) on an area of the initial pattern excluding TEG areas, so as to acquire a final pattern.

Abstract: An aspect of the disclosed embodiments is a method for printed circuit board (PCB) component placement comprising: graphically displaying, on a display device, PCB design features of a PCB design; and providing a user interface control for designating one or more of the PCB design features as electrical contacts for a first selected electrical component. Other aspects are disclosed.

Abstract: An apparatus for instantaneous generation of a pin placement quote in an injection molding process, the apparatus comprising at least a processor and a memory containing instructions configuring the at least a processor to receive part data related to at least a part from an entity, generate a pin placement schema as a function of the part data, provide a pin placement quote based on the pin placement schema, wherein providing the pin placement quote includes generating a projected part data by overlaying the pin placement schema onto the part data, determining a list of quote parameters, and formulating the pin placement quote by associating the list of quote parameters with the projected part data, and display the pin placement quote to the entity using a user interface at a display device.

Abstract: A method is disclosed herein. The method includes: providing, by an electronic design automation (EDA), a trigger signal to an application programming interface (API); providing, by the API, first parameters associated with parameterized cells in a netlist of an integrated circuit (IC); adjusting, by the API, the first parameters to generate second parameters associated with the parameterized cells in the netlist of the IC; updating, by the API, the netlist of the IC according to the second parameters; and performing, by the EDA, a simulation according to the netlist.

Abstract: According to some embodiments, the present disclosure provides a method for determining wafer inspection parameters. The method includes identifying an area of interest in an IC design layout, performing an inspection simulation on the area of interest by generating a plurality of simulated optical images from the area of interest using a plurality of optical modes, and selecting, based on the simulated optical images, at least one of the optical modes to use for inspecting an area of a wafer that is fabricated based on the area of interest in the IC design layout.

Abstract: The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and machine learning are used to train a classification that correlates the overlay error source factors with overlay metrology categories. The overlay error source factors include tool signals. The trained classification includes a base classification and a Meta classification.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes the following operations. A first layout including a plurality of first features is provided. A modified second layout is determined. The modified second layout includes a plurality of modified features separated from each other, and each of the plurality of modified features respectively overlaps each of the plurality of first features. The modified second layout is outputted to a photomask.

Abstract: A physically unclonable function (PUF) cell array includes a first PUF cell in a first column in a first direction, a second PUF cell in a second column, and a first power rail. The first PUF cell includes a first set of conductive structures that include a first conductive structure extending in the second direction and a second conductive structure extending in the first direction. The second PUF cell includes a second set of conductive structures that include a third conductive structure extending in the second direction and a fourth conductive structure extending in the first direction. The first power rail overlapping a first boundary of the first and second PUF cell. At least the first and third conductive structure, or the second and the fourth conductive structure are symmetric to each other with respect to a central line of at least the first or second PUF cell.

Abstract: A method and system for migrating an existing ASIC design from one semiconductor fabrication process to another are disclosed herein. In some embodiments, a method for migrating the existing ASIC design comprises parsing the gate-level netlist one row at a time into one or more standard cells forming the ASIC design, forming a plurality of mapping tables having mapping rules for mapping the parsed one or more standard cells into equivalent target standard cells implemented in the second semiconductor fabrication process, mapping the parsed one or more standard cells into the equivalent target standard cells using the plurality of mapping tables, and generating a target gate-level netlist describing the ASIC design in terms of the equivalent target standard cells.

Abstract: A portable information handling system glass ceramic housing integrates plural wireless charging coils on one side and plural coil interface traces on an opposing side that interface with conductive material disposed in through glass via openings. Conductive contacts interfaced with the coil interface traces and exposed at the glass ceramic housing interior couple to a printed circuit board assembly through pogo pins that bias against the conductive contacts to communicate power from the wireless charging coils to the charger of the information handling system. The conductive contacts co-locate with a logo etched into the glass ceramic housing to provide an aesthetically pleasing wireless charging solution.

Abstract: A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.

Abstract: Embodiments described herein relate to a system, software, and a method of using the system to edit a design to be printed by a lithography system. The system and methods utilize a server of a maskless lithography device. The server includes a memory. The memory includes a virtual mask file. The virtual mask file includes cells and the cells include sub-cells that form one or more polygons. The server further includes a controller coupled to the memory. The controller is configured to receive a replacement table. The replacement table includes instructions to replace the cells of the virtual mask file. The controller is further configured to replace the cells with replacement cells according to the replacement table to create an edited virtual mask file.