Patents Examined by Lex H. Malsawma
  • Patent number: 10978505
    Abstract: A hybrid-bonding-type solid-state imaging device is provided that prevents moisture from entering through the bonded interface and other areas. The solid-state imaging device includes a first interconnect structure over a sensor substrate and a second interconnect structure over a logic substrate, and the first and second interconnect structures are bonded together. At the bonded surface between the first and second interconnect structures, bonding pads formed in the first interconnect structure are bonded to bonding pads formed in the second interconnect structure. Eighth layer portions of a first seal ring formed in the first interconnect structure are bonded to eighth layer portions of a second seal ring formed in the second interconnect structure.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: April 13, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hidenori Sato, Koji Iizuka, Takeshi Kamino
  • Patent number: 10978674
    Abstract: A method of manufacturing a display apparatus includes providing a substrate, forming a display unit defining an opening portion in a display region over the substrate, forming a thin film encapsulation layer to seal the display unit, forming a touch electrode over the thin film encapsulation layer, forming a touch insulating film covering the touch electrode such that the thin film encapsulation layer and the touch insulating film are sequentially stacked and formed over the substrate in the opening portion, forming a touch contact hole by removing a portion of the touch insulating film to expose a portion of the touch electrode, and removing a portion of the touch insulating film and a portion of the thin film encapsulation layer formed in the opening portion to expose a portion of the substrate during the forming of the touch contact hole.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: April 13, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jonghyun Choi, Kinyeng Kang, Suyeon Sim
  • Patent number: 10971601
    Abstract: Replacement metal gate structures with improved chamfered workfunction metal and self-aligned contact and methods of manufacture are provided. The method includes forming a replacement metal gate structure in a dielectric material. The replacement metal gate structure is formed with a lower spacer and an upper spacer above the lower spacer. The upper spacer having material is different than material of the lower spacer. The method further includes forming a self-aligned contact adjacent to the replacement metal gate structure by patterning an opening within the dielectric material and filling the opening with contact material. The upper spacer prevents shorting with the contact material.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: April 6, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang
  • Patent number: 10972068
    Abstract: An integrated circuit (IC) device includes a first resistive strip having an input terminal and an output terminal. The IC device further includes a second resistive strip having a terminal coupled to a voltage. The second resistive strip may be coplanar with the first resistive strip. The IC device further includes a capacitor formed by the first resistive strip and the second resistive strip.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: April 6, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Chao Song, Haitao Cheng, Ye Lu, Dongjiang Qiao
  • Patent number: 10971592
    Abstract: A semiconductor device includes a gate insulating film on a semiconductor substrate, and a gate electrode on the gate insulating film. The gate electrode includes a first layer containing polycrystalline silicon, a second layer between the first layer and the gate insulating film and containing polycrystalline silicon and carbon, a third layer on an upper surface of the first layer and containing polycrystalline silicon and carbon, a fourth layer on a first side surface of the first layer and containing polycrystalline silicon and carbon, and a fifth layer on a second side surface of the first layer and containing polycrystalline silicon and carbon.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: April 6, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kazuya Fukase
  • Patent number: 10971566
    Abstract: At a bending section of a frame region, an opening portion is formed, in at least one inorganic insulating film included in the TFT layer, through the at least one inorganic insulating film to expose an upper surface of a resin substrate, and a frame wiring line is provided on the resin substrate exposed through the opening portion, and among the at least one inorganic insulating film included in the TFT layer, an inorganic insulating film being in contact with the upper surface of the resin substrate is formed with a silicon oxynitride film.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: April 6, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Takao Saitoh, Masaki Yamanaka, Yohsuke Kanzaki, Masahiko Miwa, Seiji Kaneko
  • Patent number: 10964851
    Abstract: A single light emitting diode (LED) structure includes an array of spaced discrete light emitting zones separated by isolation areas. Each emitting zone includes an epitaxial structure configured to emit an emitting light having a particular wavelength over an effective emission area. In addition, the effective emission area for each emitting zone can be geometrically defined and electrically configured to provide a desired light intensity. For example, each effective emission area can have a selected size and spacing depending on the application and light intensity requirements. Each emitting zone also includes a wavelength conversion member on its effective emission area configured to convert an emitting wavelength of the emitting light to a different color. The single (LED) structure can include multiple colors at different zones to produce a desired spectra or design.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: March 30, 2021
    Assignee: SemiLEDs Optoelectronics Co., Ltd.
    Inventors: Trung Tri Doan, David Trung Doan
  • Patent number: 10964630
    Abstract: A semiconductor device may include a first conductor plate on which a first semiconductor element, a second semiconductor element and a first circuit board are disposed, and a plurality of first signal terminals. A size of the second semiconductor is smaller than a size of the first semiconductor element. In a plan view along a direction perpendicular to the first conductor plate, the plurality of first signal terminals is located in a first direction with respect to the first semiconductor element. The second semiconductor element and the first circuit board are located between the plurality of first signal terminals and the first semiconductor element and are arranged along a second direction that is perpendicular to the first direction. A signal pad of the first semiconductor element is connected to a corresponding one of the plurality of first signal terminals via a signal transmission path of the first circuit board.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: March 30, 2021
    Assignee: DENSO CORPORATION
    Inventors: Takanori Kawashima, Makoto Imai, Masaki Aoshima
  • Patent number: 10964545
    Abstract: A semiconductor substrate processing apparatus includes a vacuum chamber having a processing zone in which a semiconductor substrate may be processed, a process gas source in fluid communication with the vacuum chamber for supplying a process gas into the vacuum chamber, a showerhead module through which process gas from the process gas source is supplied to the processing zone of the vacuum chamber, and a substrate pedestal module. The substrate pedestal module includes a pedestal made of ceramic material having an upper surface configured to support a semiconductor substrate thereon during processing, a stem made of ceramic material, and a backside gas tube made of metallized ceramic material that is located in an interior of the stem. The metallized ceramic tube can be used to deliver backside gas to the substrate and supply RF power to an embedded electrode in the pedestal.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: March 30, 2021
    Assignee: Lam Research Corporation
    Inventors: Ramkishan Rao Lingampalli, Joel Philip Hollingsworth, Bradley Baker
  • Patent number: 10950510
    Abstract: A semiconductor device includes a base substrate, a protruding structure on the base substrate, a porous film on a side surface and an upper surface of the protruding structure, and an air gap between at least a part of the side surface of the protruding structure and the porous film.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: March 16, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seok Han Park
  • Patent number: 10950739
    Abstract: A photodiode which includes a core of a first waveguide that terminates in a tapered termination that extends above a core, made of germanium or of SiGe, of a second waveguide, a matching strip that extends opposite the tapered termination on one side and opposite the core of the second waveguide on the opposite side, this matching strip being coupled optically to the core of the second waveguide by an evanescent coupling and including a first zone inside which its effective propagation index is equal to the effective propagation index of a second zone of the tapered termination, these first and second zones optically coupling the tapered termination to the matching strip through a modal coupling, and a low-index layer that extends between the matching strip and the tapered termination.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: March 16, 2021
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Karim Hassan, Salim Boutami, Christophe Kopp
  • Patent number: 10950447
    Abstract: Embodiment described herein provide a thermal treatment process following a high-pressure anneal process to keep hydrogen at an interface between a channel region and a gate dielectric layer in a field effect transistor while removing hydrogen from the bulk portion of the gate dielectric layer. The thermal treatment process can reduce the amount of threshold voltage shift caused by a high-pressure anneal. The high-pressure anneal and the thermal treatment process may be performed any time after formation of the gate dielectric layer, thus, causing no disruption to the existing process flow.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: March 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hongfa Luan, Yi-Fan Chen, Chun-Yen Peng, Cheng-Po Chau, Wen-Yu Ku, Huicheng Chang
  • Patent number: 10950822
    Abstract: A display device is provided that can increase brightness by improving light extraction efficiency. The display device can include a thin-film transistor disposed on a substrate, a first overcoat layer disposed on the thin-film transistor and including a groove portion, a reflective layer disposed on the first overcoat layer including the inside of the groove portion, a color filter disposed on the reflective layer and located in the groove portion, a second overcoat layer disposed on the color filter and the reflective layer, a first electrode disposed on the second overcoat layer and connected to the thin-film transistor, a bank layer disposed on the first electrode and including an open portion exposing the first electrode, an organic layer disposed on the bank layer and the first electrode, and a second electrode disposed on the organic film layer.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: March 16, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Kiseob Shin, Hyoungsu Kim, Doohyun Yoon
  • Patent number: 10950593
    Abstract: A package structure including a redistribution structure, a die, at least one connecting module, a first insulating encapsulant, a chip stack, and a second insulating encapsulant. The die is disposed on and electrically connected to the redistribution structure. The connecting module is disposed on the redistribution structure. The connecting module has a protection layer and a plurality of conductive bars. The conductive bars are embedded in the protection layer. The protection layer includes a plurality of openings corresponding to the conductive bars. The first insulating encapsulant encapsulates the die and the connecting module. The chip stack is disposed on the first insulating encapsulant and the die. The chip stack is electrically connected to the connecting module. The second insulating encapsulant encapsulates the chip stack.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: March 16, 2021
    Assignee: Powertech Technology Inc.
    Inventors: Shang-Yu Chang Chien, Hung-Hsin Hsu, Nan-Chun Lin
  • Patent number: 10950754
    Abstract: An embodiment discloses a semiconductor device comprising: a light-emitting structure having a first conductive semiconductor layer, a second conductive semiconductor layer and an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer; a first electrode disposed on the first conductive semiconductor layer; a second electrode disposed below the second conductive semiconductor layer; and a current blocking layer disposed between the second conductive semiconductor layer and the second electrode, wherein the first conductive semiconductor layer includes a first region in which the first electrode is disposed and a second region, the thickness of which is less than the thickness of the first region, and the current blocking layer is disposed in a region corresponding to the first region in the thickness direction.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: March 16, 2021
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Woong Sun Yum, Hyun Ju Kim, Jin Soo Park, Seung Il Lee, Jae Young Im
  • Patent number: 10943896
    Abstract: Power MOS device, in which a power MOS transistor has a drain terminal that is coupled to a power supply node, a gate terminal that is coupled to a drive node and a source terminal that is coupled to a load node. A detection MOS transistor has a drain terminal that is coupled to a detection node, a gate terminal that is coupled to the drive node and a source terminal that is coupled to the load node. A detection resistor has a first terminal coupled to the power supply node and a second terminal coupled to the detection node.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: March 9, 2021
    Assignee: STMicroelectronics S.r.l.
    Inventor: Davide Giuseppe Patti
  • Patent number: 10944070
    Abstract: A display device having improved reliability includes: a display panel including a substrate and an encapsulation layer, the substrate including a display area and a non-display area, and the encapsulation layer being located on the substrate at the display area; and a window on the display panel, and the substrate has a convex shape and has a plurality of first grooves arranged at an outer circumferential surface of the substrate.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: March 9, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Dongho Kim, Youngjin Ko, Minsoo Kim
  • Patent number: 10943846
    Abstract: A chip package structure includes a circuit structure, a redistribution structure, a heat conductive component, a chip, and a heat sink. The circuit structure includes a first circuit layer. The redistribution structure is disposed on the circuit structure and includes a second circuit layer, wherein the redistribution structure has an opening. The heat conductive component is disposed on the circuit structure and covered by the redistribution structure. The heat conductive component has a horizontal portion and a vertical portion. The horizontal portion extends toward the opening until it exceeds the opening. The vertical portion extends upward beyond the top surface of the redistribution structure from a part of the horizontal portion. The chip is disposed in the opening, and the bottom of the chip contacts the heat conductive component. The heat sink is disposed over the redistribution structure and the chip.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: March 9, 2021
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Tzu-Hsuan Wang, Chien-Chen Lin, Kuan-Wen Fong
  • Patent number: 10944073
    Abstract: The present application discloses a display panel having a display area and a peripheral area. The display panel includes a base substrate; a display unit on the base substrate; an encapsulating layer on a side of the display unit distal to the base substrate and encapsulating the display unit; and a first crack barrier layer on the base substrate and in the peripheral area and forming a first enclosure substantially surrounding a first area. The encapsulating layer includes a first inorganic sub-layer. The first inorganic sub-layer includes a first part enclosed inside the first area by the first crack barrier layer.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: March 9, 2021
    Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Weiyun Huang, Zhenxiao Tong, Wuyang Zhao, Youngyik Ko
  • Patent number: 10937680
    Abstract: Among other things a method including releasing a discrete component from an interim handle and depositing a discrete component on a handle substrate, attaching the handle substrate to the discrete component, and removing the handle substrate from the discrete component.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: March 2, 2021
    Assignee: Uniqarta, Inc.
    Inventor: Val Marinov