Abstract: A display panel includes a pad line disposed on a rear surface of a base layer and a connection line disposed on a front surface of the base layer. The pad line and the connection line are connected in an area overlapping a pad hole defined to pass through the base layer, and the pad line is connected to a driving unit on the rear surface of the base layer.

Abstract: A display device may include a first scan connection line connecting a first scan line connected to a first pixel and a first scan output transistor, a first sensing connection line connecting a first sensing line connected to the first pixel and a first sensing output transistor, the first sensing connection line crossing and overlapping the first scan connection line, a second sensing connection line connecting a second sensing line connected to a second pixel adjacent to the first pixel in a first direction and a second sensing output transistor, and a second scan connection line connecting a second scan line connected to the second pixel and a second scan output transistor, the second scan connection line crossing and overlapping the second sensing connection line.

Abstract: A method includes etching a dielectric layer of a substrate to form an opening in the dielectric layer, forming a metal layer extending into the opening, performing an anneal process, so that a bottom portion of the metal layer reacts with a semiconductor region underlying the metal layer to form a source/drain region, performing a plasma treatment process on the substrate using a process gas including hydrogen gas and a nitrogen-containing gas to form a silicon-and-nitrogen-containing layer, and depositing a metallic material on the silicon-and-nitrogen-containing layer.

Abstract: A packaged device (110) includes a substrate (114) and one or more contacts (118) disposed on a side of the substrate (114). Structures of the packaged device (110) define at least in part a recess region (120) that extends from the side of the substrate (114) and through the substrate (114), where one or more contacts (124) of a second hardware interface are disposed in the recess region (120). The one or more contacts (118) of the first hardware interface enable connection of the packaged device (110) to a printed circuit board. The one or more contacts (124) of the second hardware interface enable connection between one or more IC dies of the packaged device (110) and another IC die (150) that is a component of the packaged device (110) or of a different packaged device.

Abstract: A through via structure includes a through via and a capping pattern. The through via includes a metal pattern extending in a vertical direction, and a barrier pattern on a sidewall and a lower surface of the metal pattern. The capping pattern contacts an upper surface of the through via. A lowermost surface of an edge portion of the capping pattern is not higher than a lowermost surface of a central portion of the capping pattern.

Abstract: A display device according to an embodiment of the present invention has a first substrate, a display region provided with a plurality of pixels on the first substrate, each of the plurality of pixels including a light-emitting element, a driving circuit provided along a first direction of the display region on the first substrate, a sealing film covering the display region, and stacking a first inorganic insulating layer, an organic insulating layer, and a second inorganic insulating layer in order from the light-emitting element, a second substrate on the sealing film, a through hole provided in the first substrate, the display region, and the second substrate; and a first region surrounding the through hole.

Abstract: A semiconductor device structure is provided. The device includes one or more first semiconductor layers, and a dipole layer surrounding each first semiconductor layer of the one or more first semiconductor layers, wherein the dipole layer comprises germanium. The structure also includes a capping layer surrounding and in contact with the dipole layer, wherein the capping layer comprises silicon, one or more second semiconductor layers disposed adjacent the one or more first semiconductor layers. The structure further includes a gate electrode layer surrounding each first semiconductor layer of the one or more first semiconductor layers and each second semiconductor layer of the one or more second semiconductor layers.

Abstract: An organic light-emitting display panel, a display device, and a method of packaging a display panel are disclosed. The organic light-emitting display panel includes a cover plate, a substrate arranged opposite to the substrate, a packaging layer disposed between the cover plate and the substrate, a touch control circuit formed on the cover plate, touch bonding pins disposed at an edge of the cover plate and coupled to the touch circuit, and multiple shielding terminals disposed on both sides of the touch bonding pins. The touch bonding pins and the shielding terminals are disposed corresponding to the packaging layer. A length of each shielding terminal is consistent with a length of each touch bonding pin. Along a direction of getting away from the touch bonding pins, widths of the plurality of shielding terminals gradually decrease.

Abstract: A display substrate, a display panel, and a display device are disclosed. The display substrate includes first and second display regions and sub-pixels. The sub-pixels are divided into first-type and second-type pixel groups arranged in a second direction. The first-type pixel group includes first and second sub-pixels located in the first and second display regions. The second-type pixel group includes second sub-pixels. The second sub-pixels of at least one of the first-type and the second-type pixel groups are disposed at two sides of the first display region in a first direction. The pixel circuits corresponding to the first and second sub-pixels in one first-type pixel group are connected to one first-type data line. The pixel circuits corresponding to the second sub-pixels in one second-type pixel group are connected to one second-type data line. A power line is disposed below a first-type data line in the first display region.

Abstract: A display device that includes a substrate having a display area configured for displaying an image and a peripheral area positioned outside of the display area. A first thin film transistor is disposed on the display area. A display element is electrically connected to the first thin film transistor. The display element includes a pixel electrode, an intermediate layer, and an opposite electrode. An embedded driving circuit portion is disposed on the peripheral area. The embedded driving circuit portion includes a second thin film transistor. A common voltage supply line is disposed on the peripheral area. The common voltage supply line is positioned closer to the display area than the embedded driving circuit portion. The common voltage supply line is electrically connected to the opposite electrode.

Abstract: A display device includes a substrate including a display area and a peripheral area. A display element is disposed in the display area and is electrically connected to a thin film transistor. A power supply line is disposed in the peripheral area. An insulating layer covers a portion of the power supply line. A barrier layer is disposed on the insulating layer and includes a first side surface facing the display area and a second side surface facing away from the display area. At least one of the first side surface or the second side surface includes a concavo-convex surface. The barrier layer forms a step difference with respect to an upper surface of the insulating layer. An end of the insulating layer is positioned beyond the second side surface of the barrier layer on a side of the barrier layer facing away from the display area.

Abstract: A display device includes a display module including a first base substrate and a pad on a top surface of the first base substrate; a circuit film coupled to a lateral surface of the first base substrate and including a contact pad spaced apart from the pad; and a conductive member on the top surface of the first base substrate and in contact with the pad and the contact pad.

Abstract: In examples, a method of manufacturing a transformer device comprises providing a first magnetic member and providing a laminate member containing primary and secondary transformer windings wound around an orifice extending through the laminate member. The method further comprises positioning a build up film abutting the laminate member. The method also comprises positioning at least a portion of a second magnetic member in the orifice. The method further comprises heat pressing at least one of the first and second magnetic members such that a distance between the first and second magnetic members decreases and such that the build-up film melts, thereby producing a transformer device.

Abstract: Provided is a display device in which a defect by external light reflection is minimized in a non-display area. The display device includes a display panel and a touch unit arranged on the display panel. The display panel may include: a substrate including a display area and a non-display area arranged around the display area; an insulator including a valley portion, the valley portion being defined as an opening arranged along an outer side of the display area in the non-display area; and a display unit arranged in the display area and including a light-emitting element electrically connected to a thin film transistor. The touch unit may include a reflection prevention unit that overlaps the valley portion and is configured to reduce reflectivity of external light.

Abstract: Examples of an integrated circuit with FinFET devices and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, a gate disposed on a first side of the fin, and a gate spacer disposed alongside the gate. The gate spacer has a first portion extending along the gate that has a first width and a second portion extending above the first gate that has a second width that is greater than the first width. In some such examples, the second portion of the gate spacer includes a gate spacer layer disposed on the gate.

Abstract: Examples of an integrated circuit with FinFET devices and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, a gate disposed on a first side of the fin, and a gate spacer disposed alongside the gate. The gate spacer has a first portion extending along the gate that has a first width and a second portion extending above the first gate that has a second width that is greater than the first width. In some such examples, the second portion of the gate spacer includes a gate spacer layer disposed on the gate.

Abstract: Underfill material flow control for reduced die-to-die spacing in semiconductor packages and the resulting semiconductor packages are described. In an example, a semiconductor apparatus includes first and second semiconductor dies, each having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a common semiconductor package substrate by a plurality of conductive contacts, the first and second semiconductor dies separated by a spacing. A barrier structure is disposed between the first semiconductor die and the common semiconductor package substrate and at least partially underneath the first semiconductor die. An underfill material layer is in contact with the second semiconductor die and with the barrier structure, but not in contact with the first semiconductor die.

Abstract: Embodiments of the present disclosure disclose a display panel and a display device. The display panel includes: a base substrate, a low temperature poly-silicon semiconductor layer, an oxide semiconductor layer and a source-drain metal layer, wherein the source-drain metal layer corresponding to a bending region is provided with a plurality of mutually insulated traces extending in a first direction and arranged in a second direction; an inorganic layer between the base substrate and the source-drain metal layer, wherein the inorganic layer is provided with a groove in the bending region, and the traces are disposed above the groove; and a flexible insulating material between the inorganic layer in the bending region and the traces, wherein the flexible insulating material fills the groove.

Abstract: A method of forming an integrated circuit structure includes forming an etch stop layer over a conductive feature, forming a dielectric layer over the etch stop layer, forming an opening in the dielectric layer to reveal the etch stop layer, and etching the etch stop layer through the opening using an etchant comprising an inhibitor. An inhibitor film comprising the inhibitor is formed on the conductive feature. The method further includes depositing a conductive barrier layer extending into the opening, performing a treatment to remove the inhibitor film after the conductive barrier layer is deposited, and depositing a conductive material to fill a remaining portion of the opening.

Abstract: A method includes providing an active pattern and gate metal patterns, and inorganic insulation layers respectively therebetween in a pixel area and each extending to a bending area, providing a first photoresist pattern defining a first opening in the bending area, providing by using the first photoresist pattern, at least one of the inorganic layers in the bending area which is etched, providing a remaining photoresist pattern defining a first remaining opening corresponding to the first opening and a second opening corresponding to the active pattern, and providing by using the remaining photoresist pattern, both a contact hole corresponding to the second opening and exposing the portion of the active pattern to outside the remaining photoresist pattern, and a portion of the base substrate corresponding to the first remaining opening and exposed to outside the remaining photoresist pattern.