Patents Examined by Linda J. Fleck
  • Patent number: 5629232
    Abstract: Light emitting devices are requiring greater switching speeds to achieve greater modulation bandwidths. The problems of intrinsic capacitance associated with conventional semiconductor heterojunction devices are reduced by the reduction of pn junction capacitance as well as the use of a semi-insulating blocking layer and a conductive substrate. Furthermore, a light absorbing layer is disposed on one side of an unetched portion of the semi-insulating material and an active layer disposed on opposite side. Also, the interface of the semi-insulating material and the active and absorbing layers are at prescribed angles that reduce back reflections to the absorbing and active layers. This arrangement reduces pumping in the absorbing region and thus reduces the lasing effect, allowing for a stable LED. The angle at the interface is determined by having the structure at a predetermined crystallographic direction and having the semi-insulating mesa etched to reveal a predetermined crystalline plane.
    Type: Grant
    Filed: November 14, 1994
    Date of Patent: May 13, 1997
    Assignee: The Whitaker Corporation
    Inventor: Ching-Long Jiang
  • Patent number: 5603765
    Abstract: High breakdown voltages for AlInAs layers in InP-based devices, such as a gate layer in an InP HEMT or a collector layer in a heterojunction bipolar transistor, are achieved by growing the AlInAs layer by MBE at a substrate temperature about 70.degree.-125.degree. C. below the temperature at which a 2.times.4 reflective high energy diffraction pattern is observed. This corresponds to a growth temperature range of about 415.degree.-470.degree. C. for a 540.degree. 2.times.4 reconstruction temperature. Preferred growth temperatures within these ranges are 80.degree. C. below the 2.times.4 reconstruction temperature, or about 460.degree. C. Higher breakdown voltages are obtained than when the AlInAs layer is grown at either higher or lower temperatures.
    Type: Grant
    Filed: April 21, 1995
    Date of Patent: February 18, 1997
    Assignee: Hughes Aircraft Company
    Inventors: Mehran Matloubian, Linda M. Jelloian, Mark Lui, Takyiu Liu
  • Patent number: 5587334
    Abstract: A semiconductor laser device of low operating current and low noise for the 780 nm band to be used as the light source for an optical disc and its fabrication method. The device comprises: a certain conduction type Ga.sub.1-Y1 Al.sub.Y1 As first light guide layer, a Ga.sub.1-Y2 Al.sub.Y2 As second light guide layer of said certain conduction type, or an In.sub.0.5 Ga.sub.0.5 P or an In.sub.0.5 (GaAl).sub.0.5 P or an InGaAsP second light guide layer, successively formed one upon another at least in one side of the principal plane of an active layer; an opposite conduction type Ga.sub.1-Z Al.sub.Z As current blocking layer formed on the second light guide layer and provided with a stripe-like window; and a Ga.sub.1-Y3 Al.sub.Y3 As cladding layer of the same conduction type a said light guide layers formed on said stripe-like window, wherein relations of Z>Y3>Y2 and Y1>Y2 are established among Y1, Y2 Y3 and Z that define the AlAs mole-fractions.
    Type: Grant
    Filed: August 3, 1994
    Date of Patent: December 24, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroki Naito, Masahiro Kume, Hideyuki Sugiura, Toru Takayama, Kunio Itoh, Issei Ohta, Hirokazu Shimizu
  • Patent number: 5585306
    Abstract: In a method for producing a compound semiconductor device such as laser devices, FET and HEMT, a crystal layer is formed with materials belonging to at least two (first and second) different groups of the periodic law table under a crystal growth condition under which a value equal to the number of arrival molecules of the material of the first group having a higher vapor pressure divided by the number of arrival molecules of the material of the second group having a lower vapor pressure is equal to or less than 2.5. More preferably, this value is equal to or less than 2.0. More concretely, the crystal layer is made of V/III group elements, for example, As of group V and at least Ga of group III. Under such condition, the crystal layer can be grown with a high quality at relatively low substrate temperatures lower than 500.degree. C.
    Type: Grant
    Filed: February 8, 1994
    Date of Patent: December 17, 1996
    Assignee: Canon Kabushiki Kaisha
    Inventor: Seiichi Miyazawa
  • Patent number: 5585309
    Abstract: A method for fabricating a semiconductor laser includes forming a double heterojunction structure on a first conductivity type semiconductor substrate; forming the double heterojunction structure into a stripe mesa shape by selective etching; successively growing a first conductivity type layer, a second conductivity type current blocking layer, and a first conductivity type current blocking layer on opposite sides of the mesa to embed the mesa; and adding an impurity from a surface of the first conductivity type current blocking layer to form impurity doped regions that electrically separate the second conductivity type current blocking layer from an upper part of the mesa at opposite sides of the mesa.
    Type: Grant
    Filed: October 17, 1994
    Date of Patent: December 17, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kenzo Mori, Tadashi Kimura, Yoshitatu Kawama, Nobuaki Kaneno, Tatuya Kimura, Yuji Okura, Hitoshi Tada
  • Patent number: 5582640
    Abstract: A single crystal and a polycrystal having an excellent crystal quality and providing a highly reliable semiconductor device are formed by solid phase growth at low temperatures. An amorphous thin film is deposited on a substrate such that an average inter-atomic distance of main constituent element of the amorphous thin film is 1.02 times or more of an average inter-atomic distance of the elements in single crystal, and crystallization energy is applied to the amorphous thin film to perform solid phase growth to thereby form a single crystal.
    Type: Grant
    Filed: April 30, 1993
    Date of Patent: December 10, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takako Okada, Shigeru Kambayashi, Moto Yabuki, Shinji Onga, Yoshitaka Tsunashima, Yuuichi Mikata, Haruo Okano
  • Patent number: 5580818
    Abstract: A SiO.sub.2 mask is formed on an n-type InP substrate. The mask gap width is narrower in a region I (laser region) and wider in a region II (modulator region). With taking the mask as growth blocking masks, an optical guide layer of InGaAsP, an MQW active layer of InGaAs well layer and InGaAsP barrier layer, p-type InP layer are selectively grown. By removing a part of the mask, p-type InP clad layer and p-type InGaAs cap layer are formed. By this, regions having mutually different bandgap can be formed through one selective growth process. Also, it becomes possible to form the regions having large bandgap difference while avoiding lattice mismatching.
    Type: Grant
    Filed: April 28, 1995
    Date of Patent: December 3, 1996
    Assignee: NEC Corporation
    Inventor: Yasutaka Sakata
  • Patent number: 5573976
    Abstract: A method of fabricating a semiconductor laser includes forming an active layer including a compound semiconductor material on a semiconductor substrate, the compound semiconductor material having an energy band gap that monotonically increases as the growth temperature of the material rises above a certain growth temperature, including growing a window structure forming region including at least a region which serves as a waveguide in the proximity of a laser resonator facet at a higher temperature than a region outside the window structure forming region. Therefore, the band gap energy of the window structure forming region is larger than that of the region outside the window structure forming region. Therefore, a semiconductor laser having a window structure can easily be fabricated with a high yield and with great repeatability.
    Type: Grant
    Filed: November 9, 1995
    Date of Patent: November 12, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Manabu Kato, Takashi Motoda
  • Patent number: 5573975
    Abstract: A semiconductor device is provided that includes an optical cavity that is designed to provide a prescribed resonant optical wavelength. The optical cavity includes a mirror structure deposited on top of a substrate and a multi-layer region such as an electroabsorptive region, for example, deposited over the mirror structure. A partial antireflective coating is deposited over the multi-layer region. The mirror structure and the multilayer region have a thickness variation sufficient to yield a resonant optical wavelength that deviates from the prescribed resonant wavelength. The partial antireflective coating has a non-uniform thickness variation that causes the resonant optical wavelength to shift substantially toward the prescribed resonant optical wavelength.
    Type: Grant
    Filed: April 6, 1995
    Date of Patent: November 12, 1996
    Assignee: Lucent Technologies Inc.
    Inventors: John E. Cunningham, Keith W. Goossen
  • Patent number: 5571321
    Abstract: This disclosure herein pertains to a method for producing a GaP epitaxial wafer used for fabrication of light emitting diodes having higher brightness than light emitting diodes fabricated from a GaP epitaxial wafer produced by a conventional method have. The method comprises the steps of: preparing a GaP layered substrate 15 with one or more GaP layers on a GaP single crystal substrate 10 in the first series of liquid phase epitaxial growth; obtaining a layered GaP substrate 15a by eliminating surface irregularities of said GaP layered substrate 15 by mechano-chemical polishing to make the surface to be planar; and then forming a GaP light emitting layer composite 19 on said layered GaP substrate 15a in the second series of liquid phase epitaxial growth.
    Type: Grant
    Filed: October 20, 1994
    Date of Patent: November 5, 1996
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Munehisa Yanagisawa, Yuuki Tamura, Susumu Arisaka, Hidetoshi Matsumoto
  • Patent number: 5565031
    Abstract: Epitaxial and polycrystalline layers of silicon and silicon-germanium alloys are selectively grown on a semiconductor substrate or wafer by forming over the wafer a thin film masking layer of an oxide of an element selected from scandium, yttrium, lanthanum, cerium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium; and then growing the epitaxial layer over the wafer at temperatures below 650.degree. C. The epitaxial and polycrystalline layers do not grow on the masking layer. The invention overcomes the problem of forming epitaxial layers at temperatures above 650.degree. C. by providing a lower temperature process.
    Type: Grant
    Filed: February 17, 1995
    Date of Patent: October 15, 1996
    Assignee: International Business Machines Corporation
    Inventors: Cyril Cabral, Jr., Kevin K. Chan, Jack O. Chu, James M. E. Harper
  • Patent number: 5561080
    Abstract: A semiconductor laser of the invention includes a (100) GaAs substrate having at least one stripe groove formed on an upper face thereof, and a semiconductor multilayer structure formed on the substrate. The stripe groove extends along a <1-10> direction. The semiconductor multilayer structure includes an Al.sub.x Ga.sub.1-x As layer (0.ltoreq.x.ltoreq.1) including a portion having a surface of an (all) crystal plane (a>1), the portion being positioned on the stripe groove, a pair of AlGaInP cladding layers provided on the Al.sub.x Ga.sub.1-x As layer (0.ltoreq.x.ltoreq.1), and an active layer sandwiched between the pair of AlGaInP cladding layers.
    Type: Grant
    Filed: March 1, 1995
    Date of Patent: October 1, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akihiko Ishibashi, Isao Kidoguchi, Kiyoshi Ohnaka, Masaya Mannou
  • Patent number: 5554561
    Abstract: A vertical field effect transistor (100) and fabrication method with buried gates (104) having spaced apart gate fingers and connecting structure and overgrown with source and channel epilayer followed by a doping connection of the gate fingers and connecting structure.
    Type: Grant
    Filed: November 29, 1993
    Date of Patent: September 10, 1996
    Assignee: Texas Instruments Incorporated
    Inventor: Donald L. Plumton
  • Patent number: 5552347
    Abstract: A semiconductor pressure sensor according to the present invention includes a semiconductor substrate having a first surface, a second surface opposite to the first surface and a recess formed in the first surface, the recess defining an interior surface including a bottom surface; and a diffusion region extending from the adjacency of the bottom surface to the second surface. A pressure-sensitive resistance of the semiconductor pressure sensor is formed in the vicinity of the bottom surface of a diaphragm. Therefore, the pressure-sensitive resistance can be formed so as to be brought into alignment with the position of the diaphragm after the formation of the diaphragm. Accordingly, the semiconductor pressure sensor, which does not cause a displacement in position between the diaphragm and the pressure-sensitive resistance and has excellent accuracy, can be easily fabricated.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: September 3, 1996
    Assignee: OKI Electric Industry Co., Ltd.
    Inventors: Osamu Takano, Koji Matsumi
  • Patent number: 5550088
    Abstract: A method is disclosed for forming a self-aligned optical subassembly for supporting an optical fiber and associated optical component(s). In particular, sequential masking layer/silicon substrate etch operations are performed so as to etch, in series, the largest opening first and the narrowest opening last. By following this procedure, axial alignment between tandem grooves is maintained.
    Type: Grant
    Filed: June 2, 1993
    Date of Patent: August 27, 1996
    Assignee: Lucent Technologies Inc.
    Inventors: Mindaugas F. Dautartas, Yiu-Huen Wong
  • Patent number: 5547898
    Abstract: A method for controlling carbon doping levels in a Distributed Bragg Reflectors (DBRs) for a Vertical Cavity Surface Emitting Laser (VCSELs) devices is provided. A first stack of mirrors (105) is deposited on the surface (101) of the substrate (102). A first cladding region (106) is deposited on the first stack of mirrors (105). An active layer (108) is deposited on the first cladding layer (106). A second cladding layer (109) is deposited on the active layer (108). A second stack of mirrors (111) is deposited on the second cladding layer (109) having a carbon doping level controlled by ratio of Group V containing organometallic (tertiarybutylarsine) to Group III organometallics (trimethylgallium and trimethylaluminum).
    Type: Grant
    Filed: September 18, 1995
    Date of Patent: August 20, 1996
    Assignee: Motorola
    Inventors: Piotr Grodzinski, Hsing-Chung Lee, Chan-Long Shieh
  • Patent number: 5544618
    Abstract: An apparatus for depositing a coating on a substrate substantially eliminates the occurrence of oval defects by creating a heated tortuous path through which the source material vapors must travel before depositing on the substrate. In addition, shut-off valves for each of the source materials are positioned in the reaction chamber in close proximity to the substrate, thereby enabling layers of different compositions to be deposited with sharp transitions between adjacent layers. The apparatus may be used to efficiently coat large areas uniformly, and works equally well with either elemental or chemical source materials, or certain combinations of both. The features of the coating apparatus may be embodied in replacement source cells for retrofitting in conventional molecular beam and chemical beam epitaxy units.
    Type: Grant
    Filed: May 23, 1994
    Date of Patent: August 13, 1996
    Inventors: Richard A. Stall, Gary S. Tompa, Alexander Gurary, Craig R. Nelson
  • Patent number: 5543353
    Abstract: A semiconductor photonic integrated circuit and a manufacturing method thereof involving a selective-area growth technique using a set of insulating film patterning masks formed on a semiconductor substrate. The mask width and the mask-to-mask open space width are variable but numerically limited. A single crystal growth process is carried out to form on the same substrate a plurality of contiguous bulk semiconductor layers or quantum well layers differing from one another in terms of growth layer thickness or composition. The differences in energy level between these layers are utilized so that semiconductor photonic integrated devices of different functions are formed on the substrate.
    Type: Grant
    Filed: July 29, 1994
    Date of Patent: August 6, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Suzuki, Masahiro Aoki, Makoto Takahashi, Tsuyoshi Taniwatari
  • Patent number: 5543355
    Abstract: In a method for manufacturing a semiconductor laser device, striped grooves are formed in a compound semiconductor substrate (or crystal element) on both sides of a light emission area, Then, the compound semiconductor substrate on both outer sides of the striped grooves is etched, so that the compound semiconductor substrate is lower than at both outer sides of the striped grooves than at the light emission area. Then, Current blocking layers are buried in the compound semiconductor substrate except for the light emission area.
    Type: Grant
    Filed: April 17, 1995
    Date of Patent: August 6, 1996
    Assignee: NEC Corporation
    Inventor: Mitsuyoshi Ookubo
  • Patent number: 5538911
    Abstract: An electric device such as a light emitting device utilizing a diamond film is described. The diamond film is partially doped with an impurity selected from Group IIb or VIb of the periodic table. The doping is performed with a patterned semiconductor film as a mask in a self-aligning manner. An electrode arrangement is formed on the semiconductor film or the doped diamond film so that stability of contacts can be obtained.
    Type: Grant
    Filed: August 22, 1991
    Date of Patent: July 23, 1996
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki