Abstract: An organic light-emitting diode display panel includes a display area, a transparent area, and a wire exchange area. The display area is used for displaying an image; the transparent area is used for placing a device, and the wire exchange area is positioned at a wire connecting site between the display area and the transparent area, wherein a metal wire from the display area is electrically connected to a high light-transmissive metal wire through a via-hole at the wire exchange area, and the high light-transmissive metal wire extends to the transparent area.

Abstract: Disclosed are three-dimensional semiconductor memory devices, methods of fabricating the same, and electronic systems including the same. The device includes a substrate including a cell array region and an extension region, stack structures extending in a first direction and including gate electrodes stacked on the substrate, vertical structures penetrating the stack structures on the cell array region, a mold structure on a portion of the extension region, a first support structure extending in the first direction between the stack structures, second support structures penetrating the stack structures on the extension region and spaced apart in a second direction from the first support structure, and a third support structure surrounding the mold structure in a plan view. Respective top surfaces of ones of the second support structures and a top surface of the third support structure is higher than a top surface of ones of the vertical structures.

Abstract: A semiconductor device including a clip, and the clip includes a clip slot, and a slug and the slug includes a groove. The clip and the slug are attached by the ultrasonic welding. The groove and the clip slot are at least partially overlapping to form a gas pathway.

Abstract: A non-volatile memory chip comprises a cell region that includes a first surface, a second surface opposite to the first surface, a first cell structure, and a second cell structure spaced apart from the first cell structure; a peripheral circuit region on the first surface of the cell region, and that includes a first peripheral circuit connected to the first cell structure, a second peripheral circuit connected to the second cell structure, and a connection circuit between the first and second peripheral circuits; a through via between the first and second cell structures and that extends from the second surface of the cell region to the connection circuit of the peripheral circuit region; a redistribution layer that covers the through via on the second surface of the cell region, is connected to the through via, and extends along the second surface; and a chip pad connected to the redistribution layer.

Abstract: An integrated circuit device includes a first-type active-region semiconductor structure, a second-type active-region semiconductor structure stacked with the first-type active-region semiconductor structure, a front-side power rail in a front-side conductive layer, and a back-side power rail in a back-side conductive layer. The integrated circuit device also includes a source conductive segment intersecting the first-type active-region semiconductor structure at a source region of a transistor, a back-side power node in the back-side conductive layer, and a top-to-bottom via-connector. The source conductive segment is conductively connected to the front-side power rail through a front-side terminal via-connector. The top-to-bottom via-connector is connected between the source conductive segment and the back-side power node.

Abstract: An imaging device includes a semiconductor substrate and pixels. Each of the pixels includes a first capacitive element including a first electrode provided above the semiconductor substrate, a second electrode provided above the semiconductor substrate, and a dielectric layer located between the first electrode and the second electrode. At least one selected from the group consisting of the first electrode and the second electrode has a first electrical contact point electrically connected to a first electrical element and a second electrical contact point electrically connected to a second electrical element different from the first electrical element. The first capacitive element includes at least one trench portion having a trench shape.

Abstract: Integrated circuitry comprising an opaque material layer, such an interconnect metallization layer is first patterned with a maskless lithography to reveal an alignment feature, and is then patterned with masked lithography that aligns to the alignment feature. In some examples, the maskless lithography employs an I-line digital light processing (DLP) lithography system. In some examples the I-line DLP lithography system performs an alignment with IR illumination through a backside of a wafer. The maskless pattern may include dimensionally large windows within a frame around circuitry regions. A first etch of the opaque material layer may expose the alignment feature within the window, and a second etch of the opaque material may form IC features, such as interconnect metallization features.

Abstract: Memory structures including an MTJ-containing pillar that is void of re-sputtered bottom electrode metal particles is provided by first forming the MTJ-containing pillar on a sacrificial material-containing structure, and thereafter replacing the sacrificial material-containing structure with at least a replacement bottom electrode structure. In some embodiments, the sacrificial material-containing structure is replaced with both a bottom electrode diffusion barrier liner and a replacement bottom electrode structure.

Abstract: A semiconductor device, and a method of manufacturing the semiconductor device, includes a first source layer, a second source layer, a first insulating passivation layer partially interposed between the first source layer and the second source layer, and a gate structure located on the second source layer. The semiconductor device also includes a source contact structure passing through the gate structure, the second source layer, and the first insulating passivation layer. The source contact structure is coupled to the first source layer.

Abstract: A sensing device includes a light-emitting panel and a sensing pixel array structure. The light-emitting panel is adapted to emit an initial light with a first waveform. The sensing pixel array structure includes a plurality of first sensing pixel structures and at least one second sensing pixel structure. The first sensing pixel structures provide the initial light with the first waveform as a first sensing light to a first sensing element for sensing. The first sensing pixel structures occupy 90% or more but less than 100% of a configuration area of the overall sensing pixel array structure. The second sensing pixel structure includes a second sensing element and a light conversion layer. The second sensing pixel structure is adapted to adjust the initial light with the first waveform to a second sensing light with a second waveform to be sensed by the second sensing element.

Abstract: The present disclosure provides an electrostatic protection device, and relates to the technical field of semiconductors. The electrostatic discharge protection device includes a first P-type heavily-doped region, a first N-type heavily-doped region, a second N-type heavily-doped region, a second P-type heavily-doped region, and a third N-type heavily-doped region. The first P-type heavily-doped region and the first N-type heavily-doped region are located in a P well, the second P-type heavily-doped region and the third N-type heavily-doped region are located in a first N well, one part of the second N-type heavily-doped region is located in the P well, the other part of the second N-type heavily-doped region is located in first N well, and the P well and the first N well are adjacent to each other and both located in the P-type substrate.

Abstract: A method for forming a self-aligned double pattern and semiconductor structures are provided. The method for forming a self-aligned double pattern includes the following steps: providing a substrate; sequentially forming a first mask layer, a second mask layer and a third mask layer on an upper surface of the substrate, and etching downwards from an upper surface of the third mask layer in a direction perpendicular to the upper surface of the substrate until a first trench exposing an upper surface of the first mask layer is formed; removing the third mask layer, and partially removing the first mask layer, so as to deepen the first trench; forming a spacer layer on an inner wall of the first trench, and filling the first trench with a fourth mask layer; and partially removing the spacer layer to form a second trench exposing the substrate.

Abstract: Light emitting devices are requiring greater switching speeds to achieve greater modulation bandwidths. The problems of intrinsic capacitance associated with conventional semiconductor heterojunction devices are reduced by the reduction of pn junction capacitance as well as the use of a semi-insulating blocking layer and a conductive substrate. Furthermore, a light absorbing layer is disposed on one side of an unetched portion of the semi-insulating material and an active layer disposed on opposite side. Also, the interface of the semi-insulating material and the active and absorbing layers are at prescribed angles that reduce back reflections to the absorbing and active layers. This arrangement reduces pumping in the absorbing region and thus reduces the lasing effect, allowing for a stable LED. The angle at the interface is determined by having the structure at a predetermined crystallographic direction and having the semi-insulating mesa etched to reveal a predetermined crystalline plane.

Abstract: High breakdown voltages for AlInAs layers in InP-based devices, such as a gate layer in an InP HEMT or a collector layer in a heterojunction bipolar transistor, are achieved by growing the AlInAs layer by MBE at a substrate temperature about 70.degree.-125.degree. C. below the temperature at which a 2.times.4 reflective high energy diffraction pattern is observed. This corresponds to a growth temperature range of about 415.degree.-470.degree. C. for a 540.degree. 2.times.4 reconstruction temperature. Preferred growth temperatures within these ranges are 80.degree. C. below the 2.times.4 reconstruction temperature, or about 460.degree. C. Higher breakdown voltages are obtained than when the AlInAs layer is grown at either higher or lower temperatures.

Abstract: A semiconductor laser device of low operating current and low noise for the 780 nm band to be used as the light source for an optical disc and its fabrication method. The device comprises: a certain conduction type Ga.sub.1-Y1 Al.sub.Y1 As first light guide layer, a Ga.sub.1-Y2 Al.sub.Y2 As second light guide layer of said certain conduction type, or an In.sub.0.5 Ga.sub.0.5 P or an In.sub.0.5 (GaAl).sub.0.5 P or an InGaAsP second light guide layer, successively formed one upon another at least in one side of the principal plane of an active layer; an opposite conduction type Ga.sub.1-Z Al.sub.Z As current blocking layer formed on the second light guide layer and provided with a stripe-like window; and a Ga.sub.1-Y3 Al.sub.Y3 As cladding layer of the same conduction type a said light guide layers formed on said stripe-like window, wherein relations of Z>Y3>Y2 and Y1>Y2 are established among Y1, Y2 Y3 and Z that define the AlAs mole-fractions.

Abstract: In a method for producing a compound semiconductor device such as laser devices, FET and HEMT, a crystal layer is formed with materials belonging to at least two (first and second) different groups of the periodic law table under a crystal growth condition under which a value equal to the number of arrival molecules of the material of the first group having a higher vapor pressure divided by the number of arrival molecules of the material of the second group having a lower vapor pressure is equal to or less than 2.5. More preferably, this value is equal to or less than 2.0. More concretely, the crystal layer is made of V/III group elements, for example, As of group V and at least Ga of group III. Under such condition, the crystal layer can be grown with a high quality at relatively low substrate temperatures lower than 500.degree. C.

Abstract: A method for fabricating a semiconductor laser includes forming a double heterojunction structure on a first conductivity type semiconductor substrate; forming the double heterojunction structure into a stripe mesa shape by selective etching; successively growing a first conductivity type layer, a second conductivity type current blocking layer, and a first conductivity type current blocking layer on opposite sides of the mesa to embed the mesa; and adding an impurity from a surface of the first conductivity type current blocking layer to form impurity doped regions that electrically separate the second conductivity type current blocking layer from an upper part of the mesa at opposite sides of the mesa.

Abstract: A single crystal and a polycrystal having an excellent crystal quality and providing a highly reliable semiconductor device are formed by solid phase growth at low temperatures. An amorphous thin film is deposited on a substrate such that an average inter-atomic distance of main constituent element of the amorphous thin film is 1.02 times or more of an average inter-atomic distance of the elements in single crystal, and crystallization energy is applied to the amorphous thin film to perform solid phase growth to thereby form a single crystal.

Abstract: A SiO.sub.2 mask is formed on an n-type InP substrate. The mask gap width is narrower in a region I (laser region) and wider in a region II (modulator region). With taking the mask as growth blocking masks, an optical guide layer of InGaAsP, an MQW active layer of InGaAs well layer and InGaAsP barrier layer, p-type InP layer are selectively grown. By removing a part of the mask, p-type InP clad layer and p-type InGaAs cap layer are formed. By this, regions having mutually different bandgap can be formed through one selective growth process. Also, it becomes possible to form the regions having large bandgap difference while avoiding lattice mismatching.

Abstract: A method of fabricating a semiconductor laser includes forming an active layer including a compound semiconductor material on a semiconductor substrate, the compound semiconductor material having an energy band gap that monotonically increases as the growth temperature of the material rises above a certain growth temperature, including growing a window structure forming region including at least a region which serves as a waveguide in the proximity of a laser resonator facet at a higher temperature than a region outside the window structure forming region. Therefore, the band gap energy of the window structure forming region is larger than that of the region outside the window structure forming region. Therefore, a semiconductor laser having a window structure can easily be fabricated with a high yield and with great repeatability.