Patents Examined by Linda J. Fleck
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Patent number: 5538919Abstract: A VCSEL having a first mirror stack positioned on the surface of a substrate, an active region positioned on the first mirror stack and substantially coextensive therewith, and a second mirror stack positioned on the active region, the second mirror stack forming a ridge or mesa having a side surface. A metal contact layer is positioned on the side surface of the ridge or mesa and on portions of an end of the ridge or mesa to define a light emitting area, and a layer of diamond-like material is electrolytically plated on the metal contact layer so as to form a heat conductor to remove heat from the laser.Type: GrantFiled: May 18, 1995Date of Patent: July 23, 1996Assignee: MotorolaInventors: Michael S. Lebby, Chan-Long Shieh, Ken Davis
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Patent number: 5538915Abstract: Customizable neural network in which one or more resistors form each synapse. All the resistors in the synaptic array are identical, thus simplifying the processing issues. Highly doped, amorphous silicon is used as the resistor material, to create extremely high resistances occupying very small spaces. Connected in series with each resistor in the array is at least one severable conductor whose uppermost layer has a lower reflectivity of laser energy than typical metal conductors at a desired laser wavelength.Type: GrantFiled: June 5, 1992Date of Patent: July 23, 1996Assignee: The Regents of the University of CaliforniaInventor: Chi Y. Fu
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Patent number: 5538911Abstract: An electric device such as a light emitting device utilizing a diamond film is described. The diamond film is partially doped with an impurity selected from Group IIb or VIb of the periodic table. The doping is performed with a patterned semiconductor film as a mask in a self-aligning manner. An electrode arrangement is formed on the semiconductor film or the doped diamond film so that stability of contacts can be obtained.Type: GrantFiled: August 22, 1991Date of Patent: July 23, 1996Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Patent number: 5534444Abstract: This invention relates to a process for producing an electrically controllable matrix of vertically-structured quantum well components from a substrate on which a lower Bragg mirror has been "epitaxiated", which said mirror is made up of one or several alternations of semiconductor thin layers surmounted by an active layer consisting of compound III/V-based quantum well heterostructures, characterized in that:a) the active quantum well layer is encapsulated with a dielectric layer capable of inducing an alloy interdiffusion in the quantum well layer,b) the said dielectric layer (3) is etched in such a way as to create a self-alignment mask (4),c) the substrate covered by the self-alignment mask is treated thermally so as to create modified regions (7) by alloy interdiffusion in the active layer,d) an upper mirror (8), in semiconductor material doped inversely to the lower mirror, is deposited by epitaxial growth in the recesses of the mask with regard to the regions of the non-interdiffused active zone,e) theType: GrantFiled: June 22, 1995Date of Patent: July 9, 1996Assignee: France TelecomInventors: Yves Nissim, Marcel Bensoussan
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Patent number: 5531182Abstract: Polycrystalline silicon thin-films having a large grain size are formed by preparing a substrate of amorphous surface comprising first regions containing tin atoms at a higher content and second regions containing tin atoms at a lower content or not substantially containing them, and then heat-treating the substrate to grow crystal grains from crystal nuclei formed only in the first regions.Type: GrantFiled: May 12, 1994Date of Patent: July 2, 1996Assignee: Canon Kabushiki KaishaInventor: Takao Yonehara
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Patent number: 5527732Abstract: The invention provides a method of fabricating two dimensional semiconductor surface emitting laser and photo detector arrays for wavelength division multiplexing optical interconnections. A first stacked multiple layer structure on a first semiconductor substrate. An intermediate layer is grown on the first stacked multiple layer structure. A second stacked multiple layer structure is grown on the intermediate layer. A second semiconductor substrate is adhered on a top of the second stacked multiple layer structure by a heat treatment thereby a wafer is grown in successive growth processes to receive a selective wet etching so that the intermediate layer only is selectively etched to separate the first and second stacked multiple layer structures from one another, followed by forming surface emitting laser arrays and photo detector arrays on the first and second semiconductor substrates respectively.Type: GrantFiled: July 14, 1994Date of Patent: June 18, 1996Assignee: NEC CorporationInventors: Kenichi Kasahara, Shigeo Sugou
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Patent number: 5527425Abstract: In-containing III/V semiconductor materials (e.g., InGaP) can be dry etched in BCl.sub.3 in ECR apparatus. We have discovered that addition of N.sub.2 to the BCl.sub.3 can result in substantially higher etch rate (e.g., more than 50% higher). Etching is substantially without incubation period, and the resulting surface can be very smooth (e.g., RMS roughness less than 5 nm, even less than 2.5 nm). Exemplarily, the novel etching step is used in the manufacture of a InGaP/GaAs transistor.Type: GrantFiled: July 21, 1995Date of Patent: June 18, 1996Assignee: AT&T Corp.Inventors: William S. Hobson, John Lopata, Fan Ren
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Patent number: 5525536Abstract: A SOI substrate has a first insulating film formed on a semiconductor substrate. A first opening is formed thereon and a dummy layer is formed on the first opening and the first insulating film. A second opening is formed in the dummy layer and a second insulating film is formed and the dummy layer is removed by etching through the third opening to form a cavity. A semiconductor crystal layer is epitaxially grown within the cavity with use of the semiconductor substrate as a seed. The second insulating film is then removed from the semiconductor crystal layer.Type: GrantFiled: April 13, 1994Date of Patent: June 11, 1996Assignee: Rohm Co., Ltd.Inventor: Sigeyuki Ueda
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Patent number: 5518965Abstract: In a process for producing integrated structures having at least one cleaved optical guide, the following are successively epitaxied onto a planar surface of a monocrystalline substrate parallel to a plane of the substrate having crystal orientation <1,0,0>: an etching barrier layer for the substrate, a lower optical confinement layer, an active layer and an upper optical confinement layer. Then, the epitaxied layers are etched to form an optical guide strip having a portion oriented parallel to a first direction of crystal orientation <0,1,1> of the substrate.Type: GrantFiled: July 11, 1994Date of Patent: May 21, 1996Assignee: France TelecomInventors: Louis Menigaux, Adrien Bruno
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Patent number: 5518953Abstract: A semiconductor device is manufactured by forming an epitaxial layer (22) insulated from a silicon substrate (2), and forming a device in the epitaxial layer (22). On the semiconductor substrate (2), a silicon dioxide layer (4) is formed (FIG. 2A). Then the silicon dioxide layer (4) is provided with openings (14) (FIG. 2D). Silicon carbide is grown until it protrudes from the openings (14) to thereby form a silicon carbide seed crystal layer (16) (FIG. 2E). Next, oxidation is carried out, allowing a field oxide layer (20) to be connected at the portion under the openings (14) and the silicon carbide seed crystal layer (16) to be insulated from the silicon substrate (2). Thereafter, epitaxial growth is effected from the silicon carbide seed crystal layer (16). The growth is stopped before silicon grown layers (22) connect to one another, thus obtaining epitaxially grown layers (22) having regions which are separate from one another. The MOS device is formed in this epitaxially grown layer (22).Type: GrantFiled: March 15, 1994Date of Patent: May 21, 1996Assignee: Rohm Co., Ltd.Inventor: Hidemi Takasu
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Patent number: 5518954Abstract: A semiconductor laser capable of minimizing generation of defects at the interface between grown layers, and a method for fabricating the same.Type: GrantFiled: May 27, 1994Date of Patent: May 21, 1996Assignee: Goldstar Co., Ltd.Inventors: Tae K. Yoo, Jong S. Kim
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Patent number: 5516723Abstract: A semiconductor laser device includes a substrate having one of p- and n-conductivity types, and a current constrictive layer formed on a surface of the substrate and having the other type of conductivity. The current constrictive layer has a through-channel extending to the surface of the substrate for defining a current path in a direction perpendicular to the surface of the substrate. The through-channel is of a belt-like pattern extending in a direction perpendicular to end surfaces of the substrate. A third cladding layer having the one type of conductivity is filled in the through-channel, a surface of the third cladding layer being flush with a surface of a current constrictive layer. A first cladding layer, an active layer, and a second cladding layer which constitute a double heterostructure are formed over the third cladding layer and current constrictive layer.Type: GrantFiled: May 5, 1995Date of Patent: May 14, 1996Assignee: Sharp Kabushiki KaishaInventors: Kazuaki Sasaki, Osamu Yamamoto
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Patent number: 5514619Abstract: A semiconductor microstructure is formed by forming a groove having a surface of a side wall and a surface of a bottom, and depositing a semiconductor layer in the groove so that a width of the semiconductor layer is defined by the surface of the side wall.Type: GrantFiled: March 14, 1994Date of Patent: May 7, 1996Assignees: Matsushita Electric Industrial Co., Ltd., Optoelectronics Technology Research LaboratoryInventors: Shinichi Wakabayashi, Hitomaro Tougou, Yukio Toyoda
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Patent number: 5513593Abstract: To produce a layer by liquid-phase heteroepitaxy a molten metal serving as the solvent is saturated at a first temperature with substrate material and compounded with layer material. The solution and the substrate are then separatly "overheated" to a second, higher temperature and then brought into contact with each other. Due to the overheating a negative thermodynamic driving force results for the epitaxy which compensates the positive driving force for the epitaxy at least in part due to the different interfacial energies between layer material and solution and substrate material and solution. The degree of overheating determines the resulting total driving force for the epitaxy which may be reduced to zero. Very thin layers, down to a monolayer thickness may be grown in this way from the solution with a layer thickness exact to a monolayer with no dislocation.Type: GrantFiled: March 31, 1994Date of Patent: May 7, 1996Assignee: Max-Planck-Gesellschaft zur Foerderung der Wissenschaften e.V.Inventors: Per-Ove Hansson, Martin Albrecht
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Patent number: 5512511Abstract: A method for fabricating a two layer epitaxial structure by a liquid phase epitaxy (LPE) process, the structure being comprised of a Group II-VI semiconductor material. The method includes the steps of providing an LPE growth chamber that contains a molten Group II-VI semiconductor material 24, the molten Group II-VI semiconductor material having a first temperature (T.sub.1); growing, at the first temperature, a base layer (22) from the molten Group II-VI semiconductor material, the base layer being grown to have a first bandgap energy; employing a shutter mechanism (30) to isolate the base layer from the molten Group II-VI semiconductor material without removing the base layer from the growth chamber; reducing the first temperature of the molten Group II-VI semiconductor material to a second temperature (T.sub.Type: GrantFiled: May 24, 1994Date of Patent: April 30, 1996Assignee: Santa Barbara Research CenterInventor: Murray H. Kalisher
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Patent number: 5510291Abstract: A multi-layer mirror structure included in a surface-normal semiconductor optical cavity is fabricated in a deposition reactor dedicated to that purpose alone. Additional layers of the device are subsequently deposited on top of the mirror structure in a second reactor. In practice, the dedicated reactor produces layers whose thickness variations over their entire extents are considerably less than the thickness variations of layers made in the second reactor. This coupled with the fact that the actual achieved thickness of the mirror structure can be conveniently measured before commencing deposition of a prescribed thickness of the additional layers makes it possible to fabricate a specified-thickness optical cavity within tight tolerances in a high-yield manner.Type: GrantFiled: May 2, 1994Date of Patent: April 23, 1996Assignee: AT&T Corp.Inventor: Keith W. Goossen
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Patent number: 5508208Abstract: In a method of manufacturing diamond semiconductor mainly composed of carbon, a technique is provided which is free from the possibility of destruction of diamond structure, permits n-type doping into diamond and further permits high concentration n-type doping. In this method of diamond semiconductor manufacture, lithium atoms (which may be produced from a nitrogen compound of lithium, for instance lithium azide) is doped using ECR plasma into diamond 102 with the surface thereof having been cleaned, if necessary.Type: GrantFiled: September 27, 1994Date of Patent: April 16, 1996Assignee: Sony CorporationInventor: Junichi Sato
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Patent number: 5508225Abstract: In a method for manufacturing a semiconductor laser diode, producing visible light after growing a p type GaAs contact layer on a p type AlGaInP cladding layer, an n type layer comprising that can be selectively etched with an etchant that does not etch GaAs is grown on the p type GaAs contact layer. After cooling, the n type layer is selectively etched and removed. In this method, a diffusion potential produced at the p-n junction between the p type GaAs contact layer and the n type layer prevents ionized hydrogen from entering the p type AlGaInP cladding layer during cooling, whereby the activation ratio of Zn atoms in the p type AlGaInP cladding layer is increased. Therefore, even if the Zn/III ratio during the growth of the p type AlGaInP cladding layer is low, a semiconductor laser diode with reduced threshold current and improved temperature characteristics is attained.Type: GrantFiled: March 28, 1994Date of Patent: April 16, 1996Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Kaoru Kadoiwa
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Patent number: 5502001Abstract: Technology for forming a fine light beam having a size smaller than the theoretical limit determined by the wavelength of light and characteristics of an objective lens. A beam distribution shifter having two light transmission regions is disposed between a source of light and an objective lens, a phase shifter is provided on one of the two light transmission regions to divide the light passing through the beam distribution shifter into two light fluxes having phases opposite to each other, and the two light fluxes are focused through the objective lens to form a fine light beam having a size smaller than the theoretical limit determined by the wavelength of the light and characteristics of the objective lens due to destructive interference between the two light fluxes.Type: GrantFiled: March 28, 1994Date of Patent: March 26, 1996Assignee: Hitachi, Ltd.Inventor: Yoshihiko Okamoto
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Patent number: 5495824Abstract: A method of forming a semiconductor thin film by crystallizing a thin film crystal from an amorphous thin film. A plurality of small regions which are preferentially made nuclei generation points are formed at predetermined positions in the amorphous thin film. Solid phase growth from single nuclei formed in the small regions is preferentially effected by heating to form a crystalline semiconductor thin film in which the grain boundary positions are adjusted to the desired positions. This crystalline semiconductor thin film is subjected to a heat treatment to reduce defects in crystal grains.Type: GrantFiled: December 1, 1994Date of Patent: March 5, 1996Assignee: Canon Kabushiki KaishaInventors: Takao Yonehara, Yoshiyuki Osada