Abstract: A process is disclosed for producing a buried stripe semiconductor laser using dry etching. According to the present invention, a heterostructure is formed by a first epitaxy, during which, on a substrate is deposited a confinement layer having a first doping type, an active layer and a protection layer. The protection layer and the active layer are etched by a reactive ion beam etching method using a gaseous mixture of argon, methane and hydrogen and this takes place down to the confinement layer, so as to form a stripe from the active layer. The stripe is buried by a second epitaxy in a semiconductor layer having a second type of doping which is the opposite of the first. Particular utility is found in the area of optical telecommunications, although other utilities are contemplated.

Abstract: In a first crystal growth process for manufacturing a semiconductor laser, an n-(Al.sub.y Ga.sub.1-y).sub.0.5 In.sub.0.5 P clad layer, an undoped (Al.sub.z Ga.sub.1-z).sub.0.5 In.sub.0.5 P active layer, a p-(Al.sub.y Ga.sub.1-y).sub.0.5 In.sub.0.5 P clad layer, a p-Ga.sub.0.5 In.sub.0.5 P layer, and an n-type semiconductor layer, are sequentially stacked in the named order on an upper surface of a GaAs substrate. Thereafter, the n-type semiconductor layer is removed, and the p-Ga.sub.0.5 In.sub.0.5 P layer and the p-(Al.sub.y Ga.sub.1-y).sub.0.5 In.sub.0.5 P clad layer are selectively removed so as to form a ridge stripe. A current block layer is formed on the p-(Al.sub.y Ga.sub.-y).sub.0.5 In.sub.0.5 P clad layer at both sides of the ridge stripe, and a p-GaAs contact layer is formed on the ridge stripe and the current block layer. With this process, since the n-type semiconductor layer is formed to cover the p-Ga.sub.0.5 In.sub.0.

Abstract: An isolation structure for bipolar and CMOS circuits formed during the same processing steps to optimize the integration of bipolar and CMOS circuits. A deep trench (46) is formed in a semiconductor circuit for providing deep isolation for bipolar circuits. A shallow recess (56) is then formed, which also forms a stepped sidewall structure of the deep trench. The recess (56) and the trench (46) are covered by an insulating oxide (60), and thereafter filled with an undoped polysilicon (62) to form the different isolating structures for the different types of circuits.

Abstract: An improved semiconductor processing is disclosed. In the manufacturing process, a semiconductor layer is formed and then undergoes photo annealing. A neutralizer is then introduced to the photoannealed semiconductor. The semiconductor thus formed demonstrates the SEL effect instead of the Staebler-Wronski effect.

Abstract: A semiconductor device comprises a vertical MIS-SIT which has a smaller source-to-drain distance for operation at ultra-high speed. The semiconductor device has a substrate crystal for epitaxial growth thereon, least two semiconductor regions of different conductivity types deposited by way of epitaxial growth on the substrate crystal according to either metal organic chemical vapor deposition (MO-CVD) or molecular layer epitaxy (MLE), thereby providing a source-drain structure, a gate side formed by etching the semiconductor regions of the source-drain structure, the gate side comprising either a (111)A face or a (111)B face, and a semiconductor region deposited as a gate by way of epitaxial growth on the gate side according to either MO-CVD or MLE.

Abstract: A photoresponsive device and a method of fabricating same, wherein the device includes semiconductor material, such as a cap region (14a), comprised of elements selected from Group IIB-VIA. A molybdenum contact pad (16) is formed upon a surface of the cap region, and a molybdenum ground contact pad is formed on a surface of a base region (12). A wide bandgap semiconductor passivation layer (20) overlies the surface of cap region and also partially overlies the molybdenum contact pad. A dielectric layer (22) overlies the passivation layer, and an indium bump (24) is formed upon the molybdenum contact pad. The indium bump extends upwardly from the molybdenum contact pad and through the dielectric layer. The dielectric layer is in intimate contact with side surfaces of the indium bump such that no portion of the molybdenum contact pad can be physically contacted from a top surface of the dielectric layer.

Abstract: A semiconductor device has a thin-film resistor trimmed by laser. The semiconductor device comprises a semiconductor substrate having an element region that covers at least part of the surface of the semiconductor substrate, a first insulation film disposed on the surface of the semiconductor substrate, and a second insulation film disposed on the surface of the semiconductor substrate through an opening of the first insulation film. The opening is formed by selectively removing at least part of the first insulation film at a location on the surface of the semiconductor substrate where the element region is not involved. The thin-film resistor is formed on the second insulation film.

Abstract: A field effect transistor of the present invention has in a base layer (33) a difference in levels constituted by an upper main surface (35a) a wall surface (35b) and a lower main surface (35c), the wall surface (35b) having a gate insulating film (39) and a gate electrode (41) in a sequential order at least in a direction extending from the upper main surface (35a) to the lower main surface (35c), the wall surface (35b) being provided, on both sides of the portions thereof corresponding to the gate insulating film (39) and gate electrode (41), with inpurity diffusion regions for forming of source and drain, respectively.Accordingly, the gate electrode (41) is provided in a manner that the gate width which needs to have a relatively large size is set in a direction vertical to the upper main surface of the base layer. This makes it possible to improve the degree of integration effectively.

Abstract: A method for forming a semiconductor thin film comprises crystallizing an amorphous silicon thin film by a first thermal treatment at 700.degree. C. or lower for ten hours or longer and carrying out a second thermal treatment at 1200.degree. C. or higher in which a lamp light is radiated to the crystallized thin film.

Abstract: A semiconductor light emitting device includes a vertical aperture produced at a main surface of a semi-insulating or insulating substrate, a transverse aperture provided in the substrate communicating with the vertical aperture, a conducting semiconductor layer buried in the vertical aperture and the transverse aperture, a groove produced by etching the substrate from the surface thereof until reaching the conducting semiconductor layer at a portion of the transverse aperture, and a light emitting element produced in the groove, and the light emitting region of the element being buried in the groove and connected with the buried conducting semiconductor layer. Accordingly, no pn junction exists at the periphery of the light emitting region, and a semiconductor light emitting element of quite low parasitic capacitance is obtained at high yield. A planar structure in which two electrodes are produced at the same plane is obtained, resulting in ease of integration and enhancement of the integration density.

Abstract: The growth rate of a compound semiconductor thin film is freely enhanced or suppressed by establishing a proper temperature of a substrate 10, and by irradiating by an MOMBE technique, portions corresponding to a desired pattern on the substrate 10 with laser rays having an energy lower than that of photon which can directly decompose an organometal during film growth. A compound semiconductor thin film having a fine pattern with complicated unevenness can be formed on the substrate 10. The relative positions of the source 11 of laser rays, the optical systems 12 and 31 for irradiating the substrate with the laser rays, and the substrate 10 in the vacuum chamber 1 are maintained constant by mounting the body 1 of the MOMBE system, the source 11 of the laser rays, and the optical systems 12 and 31 for guiding the laser rays to the body 1 of the MOMBE system on a vibration proof base 30, whereby the formation of a fine pattern becomes possible.

Abstract: A method for fabricating thinned, back-illuminated, solid state image sensors 10 includes steps of positively doping a bottom surface 22 of a top semiconductor wafer 24, and bonding the bottom surface 22 of the top semiconductor wafer 24 to a top surface 26 of a bottom semiconductor wafer 28 with a silicon dioxide passivation layer 34 in between. The top wafer 24 is thinned and an insulating layer of silicon dioxide 36 and a polysilicon gate structure 38 are formed thereover. Individual dies 40 are then formed, which are bonded to a substrate 42 along each pixel face. The bottom semiconductor wafer layer 28 is etched away to expose the silicon dioxide passivation layer 34, which acts to protect the thinned top wafer layer 24. The dies 40 are then etched to expose bonding pads within the gate structure 38, and sized to create thinned, back-illuminated, solid state image sensors 10.

Abstract: Disclosed is a thin dielectric inorganic layer overlaying a substrate, and having a thickness of.ltoreq. about 20 nm and a defect density of.ltoreq. about 0.6 defects/cm.sup.2 determined by BV measurements.Also disclosed is a method of forming such a layer, according to which a layer having the desired composition and thickness is formed on a substrate, followed by an ion implantation into the substrate through the layer with a dose of.gtoreq. about 10.sup.15 ions/cm.sup.2 and a subsequent anneal at a temperature of.gtoreq. about 500.degree. C. for a predetermined time.

Abstract: A stacked floating-gate field-effect transistor ("FET") structure suitable for memory cells in a nonvolatile memory is fabricated according to a process in which a floating-gate layer is formed on a semiconductor substrate (30), oxide (42) is formed along the sidewalls (35) of the floating gate (18) extending in the channel-length direction, and an oxide-nitride-oxide ("ONO") composite layer (44) is formed along the top of the structure, including the floating gate and the sidewall oxide. The ONO composite layer and the sidewall oxide act as an isolation dielectric between the floating gate and a control gate (20) formed on top of the ONO layer.

Abstract: Described herein is a method for forming a barrier metal structure in a minute contact hole in such a way as to ensure good coverage by the metal.The method of the invention comprises the steps of: opening a contact hole in an insulation film layer on a substrate in a diameter larger than an originally intended target value; forming a barrier metal layer over the entire surfaces of the insulation film layer; forming an oxidation film layer over the entire surfaces of the barrier metal layer until the diameter of the contact hole reaches the original target value; etching the oxidation film layer by anisotropic etching; and embedding a metal in the contact hole. Further, after forming a metal plug, the barrier metal layer may be selectively etched back in such a way as to leave a barrier metal layer only at the bottom of the contact hole.

Abstract: A strain-compensated III-V quantum well device is grown by vapor phase epitaxy using the same relative atomic proportions of indium and gallium in both the quantum well layers (20) and the barrier layers (21). The top and bottom barrier layers of the quantum well stack are half the thickness of the other barrier layers of the stack.

Abstract: A method and resulting structure to provide an antifuse wherein the resistance of the programmed fuse and the line resistance and capacitance are materially reduced relative to the prior art and the procedures involved and the resulting structure of the fuse permit the use of materials not available in prior art antifuses. This is accomplished by providing the fuse on vertical sidewalls of the fuse electrode or beneath a sidewall oxide on the fuse electrode. Since the thickness of the electrode can be controlled to an extent not currently achievable by lithographic means, a much smaller area antifuse is provided using sidewall antifuse as opposed to a planar antifuse.

Abstract: A method for fabricating an optical semiconductor device includes the steps of forming at least two stripes of dielectric parallel to each other with a predetermined interval on a semiconductor substrate, growing a crystal selectively between the two stripes, and forming a multi-layer structure which is required to have a width determined by the crystal grown between the two stripes. In such a method, the width of the multi-layer structure including an active layer or a waveguide is controlled precisely, because there is no step of etching a semiconductor layer, so that the characteristics of the device may improve and the yield may increase.

Abstract: A method for manufacturing a compound semiconductor device in which a mixed crystal layer containing a III-V group compound is formed on a substrate, characterized in that when a part of the mixed crystal layer is subjected to etching by an etching liquid, the etching portion is subjected to etching while maintaining the state of not exposing light to the etching portion.

Abstract: A method for producing a field effect transistor includes depositing an insulating film on an active layer produced in a semiconductor substrate and removing a part of the insulating film, leaving a side wall substantially perpendicular to the substrate. A refractory metal is deposited on the surface of the semiconductor substrate and the insulating film. The refractory metal is removed except for a portion at the side wall of the insulating film to produce a gate electrode. A high dopant concentration region is ion implanted using the insulating film and refractory metal as a mask. The insulating film is removed and an intermediate dopant concentration region is ion implanted using the refractory metal as a mask. A source electrode is produced on the high dopant concentration region and a drain electrode is produced on the intermediate dopant concentration region. The invention may be used to produce asymmetrically doped drain and gate regions and an asymmetrically disposed gate electrode.