Patents Examined by Long K. Tran
  • Patent number: 10897093
    Abstract: In order to prevent breakage of a nut holder that holds a nut, a semiconductor apparatus includes a main terminal connected to an external conductor by a screw, a nut into which a tip of the screw is screwed, and a nut holder. The nut holder includes a recess holding the nut therein, and a peripheral wall surrounding the recess and having an opening. The peripheral wall is discontinuous at a position at which the opening is formed.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: January 19, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Takahiro Mitsumoto
  • Patent number: 10886410
    Abstract: Provided is a thin film transistor, including: a conductive light shielding layer; a metal oxide layer arranged on the light shielding layer; a buffer layer, an active layer, a gate insulating layer, a gate electrode, and an interlayer insulating layer arranged in sequence on the metal oxide layer, the interlayer insulating layer and the buffer layer comprising a first via hole and a second via hole for exposing the active layer, and a third via hole for exposing the metal oxide layer, in which a portion of the metal oxide layer exposed through the third via hole is a conductive portion, and other portions are insulative; and a source electrode and a drain electrode arranged on the interlayer insulating layer, in which the source electrode is connected to the active layer through the first via hole, and the drain electrode is connected to the active layer through the second via hole and connected to the conductive portion through the third via hole.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: January 5, 2021
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yingbin Hu, Ce Zhao, Yuankui Ding, Wei Li, Wei Song, Luke Ding, Jun Liu, Liangchen Yan
  • Patent number: 10886390
    Abstract: In a method of manufacturing a semiconductor device, a gate insulating film is formed at a first surface of a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type is formed at the first surface; a gate electrode is formed on the gate insulating film; the gate insulating film is selectively removed; a thermal oxide film is formed at a surface of the second semiconductor layer; a third semiconductor layer of the first conductivity type is selectively formed at the surface of the second semiconductor layer; an interlayer insulating film is formed on the thermal oxide film; a contact hole is selectively formed to expose the third semiconductor layer; a barrier metal is formed in the contact hole; and a metal plug is embedded in the contact hole on barrier metal by a CVD method that uses a metal halide.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: January 5, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Makoto Shimosawa
  • Patent number: 10867977
    Abstract: A display device and a method for producing a display device are disclosed. In an embodiment a display device includes a flat textile support and a plurality of optoelectronic semiconductor components disposed on the support. Each semiconductor component includes a connection substrate comprising a plurality of electrical connections, the plurality of electrical connections electrically connected via electrically conductive contact threads, wherein each electrical connection is realized by a contact hole which completely penetrates through the semiconductor component and, viewed in a plan view, is surrounded all around by the connection substrate and wherein, in each case, at least one contact thread runs through the contact hole so that the contact thread is arranged in part on an upper side of the semiconductor component facing away from the support, a plurality of semiconductor chips for generating light and at least one control unit for adjusting a color location of the light.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: December 15, 2020
    Assignee: OSRAM OLED GMBH
    Inventors: Frank Singer, Andreas Dobner
  • Patent number: 10861932
    Abstract: A semiconductor device includes a well region, a buffer region, an insulating film, an electrode, and an electric field relaxing structure. An impurity concentration in the buffer region is reduced in a direction away from the active region. An end portion of the electrode is located at a position closer to the active region than an end portion of the buffer region. The electric field relaxing structure includes a plurality of RESURF layers each surrounding the buffer region in a plan view and formed in a surface layer of the semiconductor substrate.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: December 8, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Ze Chen, Kazuhiro Shimizu
  • Patent number: 10856092
    Abstract: An acquisition system includes a processor, one or more sensors operatively coupled to the processor where the one or more sensors acquire at the ear, on the ear or within an ear canal, one or more of acceleration, blood oxygen saturation, blood pressure or heart-rate, and the one or more sensors configured to monitor a biological state or a physical motion or both for an event. The event can be a detection of a discrepancy when compared with a set of reference data by the one or more sensors or the biological state or the event can be one of a detection of an abrupt movement of a headset operatively coupled to the processor, a change in location of an earpiece operatively coupled the processor, a touching of the headset, a recognizing of a voice command, a starting or ending of a phone call, or a scheduled time.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: December 1, 2020
    Assignee: Staton Techiya, LLC
    Inventor: Steven W. Goldstein
  • Patent number: 10854612
    Abstract: A semiconductor device can include a semiconductor substrate and an active region in the semiconductor substrate, where the active region can include an oxide semiconductor material having a variable atomic concentration of oxygen. A first source/drain region can be in the active region, where the first source/drain region can have a first atomic concentration of oxygen in the oxide semiconductor material. A second source/drain region can be in the active region spaced apart from first source/drain region and a channel region can be in the active region between the first source/drain region and the second source/drain region, where the channel region can have a second atomic concentration of oxygen in the oxide semiconductor material that is less than the first atomic concentration of oxygen. A gate electrode can be on the channel region and extend between the first source/drain region and the second source/drain region.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: December 1, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Minhee Cho, Junsoo Kim, Ho Lee, Chankyung Kim, Hei Seung Kim, Jaehong Min, Sangwuk Park, Woo Bin Song, Sang Woo Lee
  • Patent number: 10854582
    Abstract: Disclosed is a light-emitting module including: a first insulation film having light transmissive property; a conductor layer provided on the first insulation film; a second insulation film disposed to face the first insulation film; a plurality of light-emitting elements interposed between the first insulation film and the second insulation film and have one surface on which a pair of electrodes connected to the conductor layer are provided; and a board that is connected to the first insulation film and has a circuit connected to the conductor layer.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: December 1, 2020
    Assignee: Toshiba Hokuto Electronics Corporation
    Inventor: Keiichi Maki
  • Patent number: 10847506
    Abstract: Disclosed is a method for fabricating a high-efficiency micro-LED module.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: November 24, 2020
    Assignee: LUMENS CO., LTD.
    Inventor: Taekyung Yoo
  • Patent number: 10833099
    Abstract: Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck having alternating conductor materials and dielectric materials and a hole containing materials extending through the conductor materials and the dielectric materials. The methods can also include forming a sacrificial material in an enlarged portion of the hole and forming a second deck of memory cells over the first deck. Additional apparatuses and methods are described.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: November 10, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Zhenyu Lu, Roger W. Lindsay, Akira Goda, John Hopkins
  • Patent number: 10830731
    Abstract: A sensor device may include a substrate, and first and second semiconductor structures arranged over the substrate. The first semiconductor structure may be an ion-sensitive field effect transistor and may include a floating gate, and a sensing element electrically coupled to the floating gate. The second semiconductor structure may be capacitively coupled to the first semiconductor structure, and may include a first diffusion region and a second diffusion region having opposite polarity type dopants, and a channel region arranged therebetween. The second semiconductor structure may be configured to receive a bias voltage to tune an electrical characteristic of the first semiconductor structure through the first diffusion region and the second diffusion region and the channel region. In some embodiments, the substrate may be a crystalline-on-insulator substrate which may be coupled to a back gate bias to reduce an effective total capacitance of the ISFET and further improve the coupling ratio.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: November 10, 2020
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Xinshu Cai, Shyue Seng Tan, Eng Huat Toh
  • Patent number: 10833058
    Abstract: A method and structure for receiving a micro device on a receiving substrate are disclosed. A micro device such as a micro LED device is punched-through a passivation layer covering a conductive layer on the receiving substrate, and the passivation layer is hardened. In an embodiment the micro LED device is punched-through a B-staged thermoset material. In an embodiment the micro LED device is punched-through a thermoplastic material.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: November 10, 2020
    Assignee: Apple Inc.
    Inventors: John A. Higginson, Andreas Bibl, Hsin-Hua Hu
  • Patent number: 10833208
    Abstract: A cover for an electronic package is manufactured by placing an optical insert, having opposite faces and configured to allow light radiation to pass therethrough, between two opposite faces of a cavity of a mold in a position such that said optical faces of the optical insert make contact with said opposite faces of the cavity of the mold. A coating material is injected into the cavity and around the optical insert. The coating material is set to obtain a substrate that is overmolded around the optical insert so as to produce the cover. An electronic package includes an electronic chip mounted to a support substrate with the cover formed by the overmolded substrate mounted to the support substrate.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: November 10, 2020
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Karine Saxod, Alexandre Mas, Eric Saugier, Gaetan Lobascio, Benoit Besancon
  • Patent number: 10825830
    Abstract: A vertical semiconductor device includes a substrate with a first and second region. A conductive pattern on the first region extends in a first direction. The first region includes a cell region, a first dummy region and a second dummy region. The conductive pattern extends in a first direction. A pad is disposed on the second region, the pad contacts a side of the conductive pattern. A plurality of first dummy structures extends through the conductive pattern on the first dummy region. A plurality of second dummy structures extend through the conductive pattern on the second dummy region, the second dummy structures disposed in a plurality of columns that extend in a second direction perpendicular to the first direction. Widths of upper surfaces of the second dummy structures are different in each column, and the widths of upper surfaces of the second dummy structures increase toward the second region.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: November 3, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae-Chul Jung, Bong-Tae Park, Jae-Joo Shim
  • Patent number: 10825957
    Abstract: A light-emitting diode includes: a semiconductor epitaxial structure including a first semiconductor layer, a second semiconductor layer disposed over the first semiconductor layer, an active layer between the first and second semiconductor layers; a first electrode electrically coupled to the first semiconductor layer and including a plurality of first sub-electrodes, wherein the plurality of first sub-electrodes are divided into one or more groups, and any two adjacent first sub-electrodes in the same group have a same projection distance; a second electrode disposed over and electrically coupled to the second semiconductor layer; a third electrode coupled to the plurality of first sub-electrodes and including one or more third sub-electrodes, wherein one of the third sub-electrodes corresponds to one of said one or more groups of the first sub-electrodes and connects first sub-electrodes in the group; and a fourth electrode coupled to the second electrode.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: November 3, 2020
    Assignee: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Gaolin Zheng, Hou-Jun Wu, Anhe He, Shiwei Liu, Kang-Wei Peng, Su-Hui Lin, Chia-Hung Chang
  • Patent number: 10818697
    Abstract: A semiconductor device includes a first TFT, a first source-side connection section that is formed from a part of a second metal film and connected to a first source region, a first drain-side connection section that is formed from a part of the second metal film and connected to a first drain region, a second TFT that is driven by the first TFT, a second source-side connection section that is formed from a part of a first metal film and connected to a second source region, and a second drain-side connection section that is formed from a part of the first metal film or a second transparent electrode film and connected to a second drain region.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: October 27, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Masahiko Suzuki, Tohru Daitoh, Hajime Imai, Tetsuo Kikuchi, Setsuji Nishimiya, Teruyuki Ueda, Masamitsu Yamanaka, Kengo Hara
  • Patent number: 10818805
    Abstract: A semiconductor sensor device includes a substrate including a first main face and a second main face opposite the first main face, a semiconductor element including a sensing region, the semiconductor element on the first main face of the substrate and being electrically coupled to the substrate, a lid on the first main face of the substrate and forming a cavity, wherein the semiconductor element is in the cavity, and a vapor deposited dielectric coating covering the semiconductor element and the first main face of the substrate, the vapor deposited dielectric coating having an opening over the sensing region, wherein the second main face of the substrate is at least partially free of the vapor deposited dielectric layer.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: October 27, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Franz-Peter Kalz, Jochen Dangelmaier
  • Patent number: 10804351
    Abstract: An organic light-emitting diode (OLED) display panel and a display device are provided. An array substrate in the OLED display panel is provided with a first retaining wall surrounding a display region of the array substrate, and a second retaining wall surrounding the first retaining wall. Multiple outer electrode lines are exposed in a gap region between the first retaining wall and the second retaining wall on the array substrate. At least one of the multiple outer electrode lines is provided with at least one outer blocking portion at an edge region on at least one side of the outer electrode line, and the outer blocking portion breaks an edge line on the side of the outer electrode line in an extending direction of the outer electrode line and in contact with the outer electrode line.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: October 13, 2020
    Assignee: SHANGHAI TIANMA AM-OLED CO., LTD.
    Inventor: Peng Zhang
  • Patent number: 10804853
    Abstract: An RF amplifier module comprises a package having a package base, at least one RF amplifier chip attached to the package base, and an RF power combiner chip attached to the package base. The RF amplifier chip comprises a substrate and at least one transistor disposed on an epilayer overlying the substrate. The substrate comprises a first layer of synthetic diamond characterized by an average value of thermal conductivity. An RF amplifier module comprises a package having a package base, at least one RF amplifier chip attached to the package base, and an RF power combiner chip attached to the package base. The RF amplifier chip comprises a substrate and at least one transistor disposed on an epilayer overlying the substrate. A first layer of synthetic diamond is at least partially disposed on top of the electronic device.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: October 13, 2020
    Assignee: Akash Systems, Inc.
    Inventors: Felix Ejeckam, Tyrone D. Mitchell, Jr., Paul Saunier
  • Patent number: 10796973
    Abstract: Structures for testing a field effect-transistor or Kelvin field-effect transistor, and methods of forming a structure for testing a field-effect transistor or Kelvin field-effect transistor. The structure includes a device-under-testing that has one or more source/drain regions and a first metallization level arranged over the device-under-testing. The first metallization level includes one or more first interconnect lines. The structure further includes a contact level having one or more first contacts arranged between the first metallization level and the device-under-testing. The one or more first contacts directly connect the one or more first interconnect lines with the one or more source/drain regions. The structure further includes a second metallization level arranged over the first metallization level. The second metallization level has a first test pad and one or more second interconnect lines connecting the one or more first interconnect lines with the first test pad.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: October 6, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Mankyu Yang, Vara Govindeswara Reddy Vakada, Edward Maciejewski, Brian Greene, Atsushi Ogino, Vikrant Chauhan, Prianka Sengupta