Patents Examined by Long K. Tran
  • Patent number: 11276742
    Abstract: A display device can include a substrate provided with a first subpixel, a first electrode including a first sub electrode provided on the first subpixel, an organic light emitting layer including first and second organic light emitting layers arranged on the first sub electrode and a second organic light emitting layer arranged on the second sub electrode, a second electrode arranged on the organic light emitting layer, and an auxiliary electrode arranged between the first organic light emitting layer on the first sub electrode and the second organic light emitting layer on the first sub electrode, wherein the auxiliary electrode is connected with the second electrode. Therefore, although the first subpixel has a two-stack structure, the organic light emitting layer can emit light in accordance with a voltage of one-stack, whereby overall power consumption can be reduced.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: March 15, 2022
    Assignee: LG DISPLAY CO., LTD.
    Inventor: JoonYoung Heo
  • Patent number: 11276702
    Abstract: Fins lined up in a Y direction, a control gate electrode and a memory gate electrode each extending in the Y direction so as to straddle the fins, a plurality of first plugs electrically connected with a drain region formed in each of the fins, and a plurality of second plugs electrically connected with a source region formed in each of the fins are formed. Here, a N-th plug of the plurality of first plugs lined up in the Y direction is coupled with each of (2N?1)-th and 2N-th fins in the Y direction. Also, a N-th plug of the plurality of second plugs lined up in the Y direction is coupled with each of 2N-th and (2N+1)-th fins in the Y direction.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: March 15, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yoshiyuki Kawashima
  • Patent number: 11271034
    Abstract: A method of manufacturing a plurality of magnetoresistive memory element having a dielectric thermal buffer layer between a thin top electrode of the magnetic tunnel junction (MTJ) element and a bit line, and a bit-line VIA electrically connecting the top electrode and the bit line having a vertical distance away from the location of the MTJ stack. In a laser thermal annealing, a short wavelength of a laser has a shallow thermal penetration depth and a high thermal resistance from the bit line to the MTJ stack only causes a temperature rise of the MTJ stack being much smaller than that of the bit line. As the temperature of the MTJ element during the laser thermal annealing of bit line copper layer is controlled under 300-degree C., possible damages on MTJ and magnetic property can be avoided.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: March 8, 2022
    Inventor: Yimin Guo
  • Patent number: 11264546
    Abstract: A metallic structure for an optical semiconductor device, including a base body having disposed thereon at least in part metallic layers in the following order; a nickel or nickel alloy plated layer, a gold or gold alloy plated layer, and a silver or silver alloy plated layer, wherein the silver or silver alloy plated layer has a thickness in a range of 0.001 ?m or more and 0.01 ?m or less.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: March 1, 2022
    Assignee: NICHIA CORPORATION
    Inventors: Yasuo Kato, Kazuya Matsuda
  • Patent number: 11257839
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. A stack comprising vertically-alternating first tiers and second tiers is formed above the conductor tier. The stack comprises laterally-spaced memory-block regions that have horizontally-elongated trenches there-between. Channel-material strings extend through the first tiers and the second tiers. Material of the first tiers is of different composition from material of the second tiers. A lowest of the first tiers comprises sacrificial material of different composition from the first-tier material there-above and from the second-tier material tier there-above. The sacrificial material is of different composition from that of an uppermost portion of the conductor material of the conductor tier.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: February 22, 2022
    Assignee: Micron Technology, Inc.
    Inventor: John D. Hopkins
  • Patent number: 11251315
    Abstract: A method of fabricating a solar cell can include forming a dielectric region on a silicon substrate. The method can also include forming an emitter region over the dielectric region and forming a dopant region on a surface of the silicon substrate. In an embodiment, the method can include heating the silicon substrate at a temperature above 900 degrees Celsius to getter impurities to the emitter region and drive dopants from the dopant region to a portion of the silicon substrate.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: February 15, 2022
    Assignee: SunPower Corporation
    Inventors: David D. Smith, Tim Dennis, Russelle De Jesus Tabajonda
  • Patent number: 11239376
    Abstract: The present disclosure relates to a structure comprising, in a trench of a substrate, a first conductive region separated from the substrate by a first distance shorter than approximately 10 nm; and a second conductive region extending deeper than the first region.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: February 1, 2022
    Assignee: STMicroelectronics (Tours) SAS
    Inventor: Frederic Lanois
  • Patent number: 11233209
    Abstract: An imaging device including a semiconductor substrate having a pixel region where pixels are arranged and a peripheral region adjacent to the pixel region; an insulating layer that covers the pixel region and the peripheral region; a first electrode that is located on the insulating layer above the pixel region; a photoelectric conversion layer that covers the first electrode; and a first layer that covers the photoelectric conversion layer, the first layer being located above the pixel region and the peripheral region. The thickness of the first layer above the peripheral region is larger than a thickness of the first layer above the pixel region, and a level of an uppermost surface of the first layer above the peripheral region is higher than a level of an uppermost surface of the first layer above the pixel region.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: January 25, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shunsuke Isono, Akio Nakajun
  • Patent number: 11227760
    Abstract: A wafer thinning method and a wafer structure are provided. In the wafer thinning method, a to-be-thinned wafer is provided, and the to-be-thinned wafer is grinded on a rear surface of the to-be-thinned wafer. Then, a first planarization process is performed on a rear surface of the grinded wafer to restore surface flatness of the grinded wafer, and a second planarization process is performed on a rear surface of the wafer obtained after the first planarization process is performed until a target thinned thickness is reached.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: January 18, 2022
    Assignee: Wuhan Xinxin Semiconductor Manufacturing Co., Ltd.
    Inventor: Hongsheng Yi
  • Patent number: 11217589
    Abstract: A semiconductor device includes a first vertical transistor, a second vertical transistor adjacent to the first vertical transistor, and an air gap inserted between the first vertical transistor and the second vertical transistor. The first vertical transistor includes a first channel region, a first word line wrapping the first channel region, and a first word line dielectric layer between the first channel region and the first word line. The second vertical transistor includes a second channel region, a second word line wrapping the second channel region, and a second word line dielectric layer between the second channel region and the second word line. The first word line and the second word line respectively have a top width and a bottom width, and the top width is greater than the bottom width.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: January 4, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Jhen-Yu Tsai
  • Patent number: 11211553
    Abstract: An integrated circuit (IC) device includes a logic portion including logic circuits in multiple vertically stacked metal layers interconnected by one or more via layers, and a memory portion with a plurality of magnetoresistive devices. Each magnetoresistive device is provided in a single metal layer of the multiple vertically stacked metal layers of the IC device.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: December 28, 2021
    Assignee: Everspin Technologies, Inc.
    Inventors: Sanjeev Aggarwal, Kerry Joseph Nagel
  • Patent number: 11189653
    Abstract: A semiconductor device includes a pixel array comprising a first pixel and a second pixel. The semiconductor device includes a metal structure overlying a portion of a substrate between the first pixel and the second pixel. The semiconductor device includes a first barrier layer adjacent a sidewall of the metal structure. The semiconductor device includes a passivation layer adjacent a sidewall of the first barrier layer. The first barrier layer is between the passivation layer and the metal structure.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: November 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Ya Chun Teng, Yun-Wei Cheng, Chien Ming Sung
  • Patent number: 11183477
    Abstract: Embodiments include a mixed hybrid bonding structure comprising a composite dielectric layer, where the composite dielectric layer comprises an organic dielectric material having a plurality of inorganic filler material. One or more conductive substrate interconnect structures are within the composite dielectric layer. A die is on the composite dielectric layer, the die having one or more conductive die interconnect structures within a die dielectric material. The one or more conductive die interconnect structures are directly bonded to the one or more conductive substrate interconnect structures, and the inorganic filler material of the composite dielectric layer is bonded to the die dielectric material.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: November 23, 2021
    Assignee: Intel Corporation
    Inventors: Shawna Liff, Adel Elsherbini, Johanna Swan, Nagatoshi Tsunoda, Jimin Yao
  • Patent number: 11177457
    Abstract: A display apparatus includes a substrate, an element layer, a protective film, a mechanical member, a first adhesive layer and a second adhesive layer. An opening of the protective film is located between a first portion of the protective film and a second portion of the protective film. The first portion of the protective film, the second portion of the protective film and the opening of the protective film are respectively overlapped with a first portion of the substrate, a second portion of the substrate and a third portion of the substrate. The first adhesive layer and the second adhesive layer are respectively disposed on a first surface and a second surface of the mechanical member. The third portion of the substrate is connected between the first portion of the substrate and the second portion of the substrate, and the third portion of the substrate is bent.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: November 16, 2021
    Assignee: Au Optronics Corporation
    Inventors: Chih-Tsung Lee, Zih-Shuo Huang, Yi-Wei Tsai, Ko-Chin Chung, Ming-Chang Hsu, Heng-Chia Hsu
  • Patent number: 11164892
    Abstract: A semiconductor-on-insulator (SOI) device including a handle wafer, a buried oxide (BOX), and a top device layer is provided. A plurality of elongated trenches are formed in the handle wafer. Air gaps are formed in the elongated trenches by pinching off each of the elongated trenches. In one approach, prior to the pinching off, a plurality of lateral openings are formed contiguous with the elongated trenches and adjacent to the BOX. The elongated trenches and/or the lateral openings reduce parasitic capacitance between the handle wafer and the top device layer. In another approach, sidewalls of the elongated trenches are implant-damaged so as to further reduce the parasitic capacitance between the handle wafer and the top device layer.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: November 2, 2021
    Assignee: Newport Fab, LLC
    Inventor: Paul D. Hurwitz
  • Patent number: 11152499
    Abstract: A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer; a second nitride semiconductor layer having a greater band gap than the first nitride semiconductor layer; a source electrode and a drain electrode on the second nitride semiconductor layer apart from each other; a third nitride semiconductor layer, between the source electrode and the drain electrode, containing a p-type first impurity and serving as a gate; and a fourth nitride semiconductor layer, between the third nitride semiconductor layer and the drain electrode, containing a p-type second impurity, wherein the average carrier concentration of the fourth nitride semiconductor layer is lower than the average carrier concentration of the third nitride semiconductor layer.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: October 19, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hideyuki Okita, Manabu Yanagihara, Takahiro Sato, Masahiro Hikita
  • Patent number: 11152547
    Abstract: A metallic structure for an optical semiconductor device including a conductive base body having disposed thereon metallic layers in the following order: a nickel or nickel alloy plated layer, a gold or gold alloy plated layer, and an indium or indium alloy plated layer, wherein the indium or indium alloy plated layer has a thickness in a range of 0.002 ?m or more and 0.3 ?m or less.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: October 19, 2021
    Assignee: NICHIA CORPORATION
    Inventors: Yasuo Kato, Kazuya Matsuda
  • Patent number: 11145627
    Abstract: Provided is a semiconductor package including first to third semiconductor dies, first to third RDL layers, conductive vias and an encapsulant, and a manufacturing method thereof. The first RDL layer is on an active surface of the first semiconductor die. The second semiconductor die is on the first RDL layer and electrically connected thereto through first TSVs. The conductive vias are on the first RDL layer and around the second semiconductor die. The encapsulant encapsulates the second semiconductor die and the conductive vias. The second RDL layer is on the encapsulant. The third semiconductor die is on the second RDL layer and electrically connected thereto through second TSVs. The third RDL layer is on the third semiconductor die. The area of the second semiconductor die is smaller than that of the first semiconductor die. The area of the third semiconductor die is larger than that of the second semiconductor die.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: October 12, 2021
    Assignee: Winbond Electronics Corp.
    Inventor: Jin-Neng Wu
  • Patent number: 11145690
    Abstract: A memory device includes a dielectric layer, a bottom electrode, an inter-metal dielectric (IMD) layer, a phase change element in the IMD layer, and a top electrode. The bottom electrode is in the dielectric layer. The IMD layer is over first dielectric layer. The phase change element is in the IMD layer. The top electrode is over the phase change element and is separated from the dielectric layer by at least an air gap free of materials of the IMD layer and the phase change element.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: October 12, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jau-Yi Wu
  • Patent number: 11121147
    Abstract: A semiconductor storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a contact plug, a memory trench extending between the second conductive layer and the third conductive layer. The memory trench is formed around the contact plug, and surrounds a first area in which the contact plug is disposed. A second area is separated from the first area and includes a pillar penetrating the first conductive layer. The second conductive layer extends between the first and second areas, and is connected to the first conductive layer. The third conductive layer is on the opposite side of the first area to the second area, and is connected to the first conductive layer.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: September 14, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Keisuke Nakatsuka, Yoshitaka Kubota, Tetsuaki Utsumi, Yoshiro Shimojo, Ryota Katsumata