Patents Examined by Long K. Tran
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Patent number: 11004938Abstract: A semiconductor substrate structure includes: a substrate; and an epitaxial growth layer bonded to the substrate, wherein the substrate and the epitaxial growth layer are bonded by a room-temperature bonding or a diffusion bonding.Type: GrantFiled: May 29, 2019Date of Patent: May 11, 2021Assignee: ROHM CO., LTD.Inventors: Takuji Maekawa, Mitsuru Morimoto, Makoto Takamura
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Patent number: 10985153Abstract: According to one embodiment, a semiconductor device includes: a printed wiring substrate that includes a substrate, a wiring layer on the substrate, and a first insulating layer on the wiring layer. The wiring layer includes a connection terminal and a wiring electrically connected to the connection terminal. The first insulating layer includes an opening that exposes at least a portion of the connection terminal and at least a portion of the wiring, and at least one of a protrusion portion or a recess portion, provided along an edge of the opening, that overlaps the wiring. The semiconductor device includes a semiconductor chip mounted on the printed wiring substrate; a bonding wire that electrically connects the connection terminal and the semiconductor chip; and a second insulating layer that covers the semiconductor chip, the bonding wire, and the opening.Type: GrantFiled: September 3, 2019Date of Patent: April 20, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventor: Takahiro Mori
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Patent number: 10978509Abstract: The present invention provides a display panel and a method of manufacturing the same. The display panel employs a target light transmission layer disposed on a target light conversion layer for transmitting the target light generated by the target light conversion layer and reflecting the excitation light passing through the target light conversion layer, such that the target light emitted by the sub-pixel units is mixed with a small amount of excitation light or even without excitation light, so that the target light emitted by the sub-pixel units is relatively pure, thereby solving the technical problem that the existing micro-display technology has defects.Type: GrantFiled: April 17, 2019Date of Patent: April 13, 2021Inventors: Guiyang Zhang, Guowei Zha
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Patent number: 10978356Abstract: A method of forming a semiconductor structure includes forming a recess within a semiconductor substrate, the recess is located between adjacent fins of a plurality of fins on the semiconductor substrate, forming a first liner above a perimeter including the recess, top surfaces of the semiconductor substrate, and top surfaces and sidewalls of the plurality of fins, the first liner includes a first oxide material, forming a second liner directly above the first liner, and forming a third liner directly above the second liner, the third liner includes a nitride material, the second liner includes a second oxide material capable of creating a dipole effect that neutralizes positive charges generated within the third liner and between the third liner and the first liner.Type: GrantFiled: May 10, 2019Date of Patent: April 13, 2021Assignee: International Business Machines CorporationInventors: Choonghyun Lee, Xin Miao, Alexander Reznicek, Jingyun Zhang
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Patent number: 10964867Abstract: Embodiments relate to using flux or underfill as a trapping layer for temporarily attaching light emitting diodes (LEDs) to a substrate and heating to simultaneously bond multiple LEDs onto the substrate. The flux or underfill may be selectively coated at the ends of electrodes of the LEDs prior to placing the LEDs on the substrate. Due to adhesive properties of the flux or underfill, multiple LEDs can be placed on and attached to the substrate prior to performing the bonding process. Once LEDs are placed on the substrate, the flux or underfill facilitates formation of metallic contacts between electrodes of the LED and contacts of the substrate during the bonding process. By using the flux or underfill, the formation of metallic contacts can be performed even without applying pressure.Type: GrantFiled: May 29, 2019Date of Patent: March 30, 2021Assignee: Facebook Technologies, LLCInventors: Daniel Brodoceanu, Thiago Martins Amaral, Pooya Saketi, Patrick Joseph Hughes, Alexander Udo May, Karsten Moh, Oscar Torrents Abad
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Patent number: 10957670Abstract: An electronic component module includes a semiconductor package having a first surface provided as a mounting surface and a second surface opposing the first surface, and including a semiconductor chip, a component package having a first surface facing the second surface of the semiconductor package, and a second surface opposing the first surface of the component package, the component package including a passive component, and a connector disposed on the second surface of the component package and having a connection surface configured to be mechanically coupled to an external device, the connector including a plurality of connection lines arranged on the connection surface.Type: GrantFiled: August 14, 2019Date of Patent: March 23, 2021Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Hyung Joon Kim, Seok Hwan Kim, Sung Il Jo, Jung Ho Shim
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Patent number: 10937790Abstract: A semiconductor device includes a first bit line disposed over a semiconductor substrate. The semiconductor device also includes a capacitor contact and a dielectric structure disposed over the semiconductor substrate and adjacent to the first bit line. The capacitor contact, the dielectric structure and the first bit line are separated from one another by an air gap structure.Type: GrantFiled: August 14, 2019Date of Patent: March 2, 2021Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Kuo-Hui Su
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Patent number: 10930693Abstract: A semiconductor device includes a substrate having a first surface and a second surface opposite to the first surface. A device isolation layer which defines a first region, a second region, and a support region in the substrate. The second region has a smaller width than the first region, and the support region is between the first region and the second region. A photoelectric conversion element is in the first region. The support region is continuous with the first region and the second region. The device isolation layer has an integral insulation structure which extends through the substrate from the first surface of the substrate to the second surface of the substrate.Type: GrantFiled: August 14, 2019Date of Patent: February 23, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae Kyu Lee, Ji Yoon Kim, Seung Sik Kim, Min Woong Seo, Ji Youn Song
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Patent number: 10930884Abstract: An organic light-emitting display device includes a substrate and a display area over the substrate. The display area includes a plurality of organic light-emitting diodes each including a first electrode, an emission layer, and a second electrode. A first power supply line is located outside the display area and is configured to supply power to the plurality of organic light-emitting diodes. A protective portion is disposed on an end of the first power supply line facing away from the display area. An encapsulation unit includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer. The encapsulation unit is positioned in the display area. A dam unit is arranged between the first inorganic encapsulation layer and the second inorganic encapsulation layer. The dam unit is disposed on an end of the organic encapsulation layer facing away from the display area.Type: GrantFiled: January 30, 2019Date of Patent: February 23, 2021Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Seungmin Lee, Taehyun Kim, Donghwan Shim, Jungkyu Lee
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Patent number: 10923686Abstract: A heat dissipation structure for a flexible display is disclosed, and includes: a substrate, an anode metal layer, light emitting diode elements, a pixel defining layer, a cathode metal layer, and a heat conducting insulator disposed in sequence. The pixel defining layer has grooves, and the heat conducting insulator is sandwiched between the anode metal layer and the cathode metal layer, and disposed in the grooves. The heat conducting insulator is used to connect the anode metal layer and the cathode metal layer, so as to form an electrically insulating and thermally conducting path between the anode metal layer and the cathode metal layer.Type: GrantFiled: January 17, 2019Date of Patent: February 16, 2021Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.Inventors: Ying Wan, Sheng Liu
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Patent number: 10923525Abstract: A complementary metal oxide semiconductor (CMOS) device embedded with micro-electro-mechanical system (MEMS) components in a MEMS region. The MEMS components, for example, are infrared (IR) thermosensors. The device is encapsulated with a CMOS compatible IR transparent cap to hermetically seal the MEMS sensors in the MEMS region. The CMOS cap includes a base cap with release openings and a seal cap which seals the release openings.Type: GrantFiled: March 5, 2020Date of Patent: February 16, 2021Assignee: Meridian Innovation Pte LtdInventors: Wan Chia Ang, Piotr Kropelnicki, Ilker Ender Ocak, Paul Simon Pontin
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Patent number: 10923638Abstract: An electronic device includes a carrier substrate having a front face and an electronic chip mounted on the front face. An encapsulation cover is mounted above the front face and bounds a chamber in which the chip is situated. A front opening is provided in front of an optical component of the chip. An optical element, designed to allow light to pass, is mounted on the cover in a position which covers the front opening of the cover. The optical element includes a central region designed to deviate light and a positioning pattern that is visible through the front opening. An additional mask is mounted on the encapsulation cover in a position which extends in front of the optical element. A local opening of the additional mask is situated in front of the optical component.Type: GrantFiled: September 17, 2019Date of Patent: February 16, 2021Assignee: STMicroelectronics (Grenoble 2) SASInventors: Nicolas Mastromauro, Karine Saxod
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Patent number: 10916652Abstract: Asymmetric transistors and related methods and devices are disclosed. A transistor includes a semiconductor material doped with a first type of charge carriers along the gate oxide according to an asymmetric doping profile with a halo region on a source side. The transistor also includes a source including a lightly doped drain (LDD) on the source side, and a drain having a doping profile of charge carriers of a second type graded in a decreasing manner toward the source side. A method includes applying a large angle tilt implant drain (LATID) process to a drain side, a halo implant process to a source side, and applying an LDD process on the source side. A memory device includes an asymmetric transistor. A computing device includes an asymmetric transistor.Type: GrantFiled: December 28, 2016Date of Patent: February 9, 2021Assignee: Intel CorporationInventor: Yen Chun Lee
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Patent number: 10903449Abstract: The organic electroluminescence display device of an embodiment of the present invention includes a substrate, a plurality of pixels formed on the substrate, and a sealing film that covers the plurality of pixels. The sealing film includes a first barrier layer, a base layer covering the top surface of the first barrier layer, an inter layer locally formed on the top surface of the base layer, and a second barrier layer covering the top surface of the base layer and the top surface of the inter layer. The inter layer is formed so as to cover a step on the top surface of the base layer.Type: GrantFiled: May 12, 2020Date of Patent: January 26, 2021Assignee: Japan Display Inc.Inventor: Akinori Kamiya
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Patent number: 10903262Abstract: Device and method of forming the device are disclosed. The method includes providing a substrate prepared with a complementary metal oxide semiconductor (CMOS) region and a sensor region. A substrate cavity is formed in the substrate in the sensor region, the substrate cavity including cavity sidewalls and cavity bottom surface and a membrane which serves as a substrate cavity top surface. The cavity bottom surface includes a reflector. The method also includes forming CMOS devices in the CMOS region, forming a micro-electrical mechanical system (MEMS) component on the membrane, and forming a back-end-of-line (BEOL) dielectric disposed on the substrate having a plurality of interlayer dielectric (ILD) layers. The BEOL dielectric includes an opening to expose the MEMS component. The opening forms a BEOL cavity above the MEMS component.Type: GrantFiled: July 21, 2019Date of Patent: January 26, 2021Assignee: Meridian Innovation Pte LtdInventors: Piotr Kropelnicki, Ilker Ender Ocak, Paul Simon Pontin
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Patent number: 10897093Abstract: In order to prevent breakage of a nut holder that holds a nut, a semiconductor apparatus includes a main terminal connected to an external conductor by a screw, a nut into which a tip of the screw is screwed, and a nut holder. The nut holder includes a recess holding the nut therein, and a peripheral wall surrounding the recess and having an opening. The peripheral wall is discontinuous at a position at which the opening is formed.Type: GrantFiled: July 1, 2019Date of Patent: January 19, 2021Assignee: FUJI ELECTRIC CO., LTD.Inventor: Takahiro Mitsumoto
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Patent number: 10886410Abstract: Provided is a thin film transistor, including: a conductive light shielding layer; a metal oxide layer arranged on the light shielding layer; a buffer layer, an active layer, a gate insulating layer, a gate electrode, and an interlayer insulating layer arranged in sequence on the metal oxide layer, the interlayer insulating layer and the buffer layer comprising a first via hole and a second via hole for exposing the active layer, and a third via hole for exposing the metal oxide layer, in which a portion of the metal oxide layer exposed through the third via hole is a conductive portion, and other portions are insulative; and a source electrode and a drain electrode arranged on the interlayer insulating layer, in which the source electrode is connected to the active layer through the first via hole, and the drain electrode is connected to the active layer through the second via hole and connected to the conductive portion through the third via hole.Type: GrantFiled: April 24, 2019Date of Patent: January 5, 2021Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Yingbin Hu, Ce Zhao, Yuankui Ding, Wei Li, Wei Song, Luke Ding, Jun Liu, Liangchen Yan
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Patent number: 10886390Abstract: In a method of manufacturing a semiconductor device, a gate insulating film is formed at a first surface of a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type is formed at the first surface; a gate electrode is formed on the gate insulating film; the gate insulating film is selectively removed; a thermal oxide film is formed at a surface of the second semiconductor layer; a third semiconductor layer of the first conductivity type is selectively formed at the surface of the second semiconductor layer; an interlayer insulating film is formed on the thermal oxide film; a contact hole is selectively formed to expose the third semiconductor layer; a barrier metal is formed in the contact hole; and a metal plug is embedded in the contact hole on barrier metal by a CVD method that uses a metal halide.Type: GrantFiled: July 1, 2019Date of Patent: January 5, 2021Assignee: FUJI ELECTRIC CO., LTD.Inventor: Makoto Shimosawa
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Patent number: 10867977Abstract: A display device and a method for producing a display device are disclosed. In an embodiment a display device includes a flat textile support and a plurality of optoelectronic semiconductor components disposed on the support. Each semiconductor component includes a connection substrate comprising a plurality of electrical connections, the plurality of electrical connections electrically connected via electrically conductive contact threads, wherein each electrical connection is realized by a contact hole which completely penetrates through the semiconductor component and, viewed in a plan view, is surrounded all around by the connection substrate and wherein, in each case, at least one contact thread runs through the contact hole so that the contact thread is arranged in part on an upper side of the semiconductor component facing away from the support, a plurality of semiconductor chips for generating light and at least one control unit for adjusting a color location of the light.Type: GrantFiled: November 9, 2018Date of Patent: December 15, 2020Assignee: OSRAM OLED GMBHInventors: Frank Singer, Andreas Dobner
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Patent number: 10861932Abstract: A semiconductor device includes a well region, a buffer region, an insulating film, an electrode, and an electric field relaxing structure. An impurity concentration in the buffer region is reduced in a direction away from the active region. An end portion of the electrode is located at a position closer to the active region than an end portion of the buffer region. The electric field relaxing structure includes a plurality of RESURF layers each surrounding the buffer region in a plan view and formed in a surface layer of the semiconductor substrate.Type: GrantFiled: July 18, 2019Date of Patent: December 8, 2020Assignee: Mitsubishi Electric CorporationInventors: Ze Chen, Kazuhiro Shimizu