Abstract: A method for fabricating a semiconductor device, wherein the method comprises steps as follows: A dummy gate with a poly-silicon gate electrode and a passive device having a poly-silicon element layer are firstly provided. A hard mask layer is then formed on the dummy gate and the passive device. Next, a first etching process is performed to remove a portion of the hard mask layer to expose a portion of the poly-silicon element layer. Subsequently, an inner layer dielectric (ILD) is formed on the dummy gate and the poly-silicon element layer, and the ILD is flattened by using the hard mask layer as a polishing stop layer. Thereafter, a second etching process is performed to remove the poly-silicon gate electrode, and a metal gate electrode is formed on the location where the poly-silicon gate electrode was initially disposed.

Abstract: The disclosure is related to a thin film transistor and a method of manufacturing the thin film transistor. The thin film transistor comprises a substrate, a gate, a gate insulation layer, a first semiconductor layer, an etch stop layer and a second semiconductor layer sequentially stacked on a surface of the substrate, and a source and a drain formed separating from each other and the source and the drain overlapping two ends of the second semiconductor layer respectively. A first via and a second via are formed on the etch stop layer corresponding to the source and the drain respectively. The source connects the first semiconductor layer through the first via; the drain connects the first semiconductor layer through the second via. The thin film transistor of the disclosure can effectively increase the on-state current of the thin film transistor and have a faster switching speed.

Abstract: Embodiments of the invention provides a light emitting device, which comprises a backplane, an encapsulating structure, and a light emitting structure and a scattering layer disposed between the backplane and the encapsulating structure; the scattering layer is located on the light exiting side of the light emitting structure; the light emitting structure is isolated into a plurality of light emitting units, the scattering layer is isolated into a plurality of scattering units, and the plurality of light emitting units correspond to the plurality of scattering units one to one; wherein each of the light emitting units comprises a first light emitting sub-unit, a second light emitting sub-unit and a third light emitting sub-unit. The embodiments of the invention may be used for a display device and a lighting lamp, thereby increasing the light emitting area and achieving uniform mixed emergent light.

Abstract: An apparatus is described that includes a substrate and a mold compound disposed on the substrate. The semiconductor die is embedded within the mold compound and is electrically coupled to lands on the substrate. Solder balls are disposed around the semiconductor die on the substrate. Each of the solder balls have a solid coating thereon. The solid coating contains a cleaning agent to promote its solder ball's coalescence with another solder ball. Respective vias are formed in the mold compound that expose the solder balls and their respective solid coatings. In combined or alternate embodiments outer edges of the mold compound have smaller thickness than regions of the mold compound between the vias and the semiconductor die. In combined or alternate embodiments micro-channels exist between the solder balls and the mold compound.

Abstract: A display device including a data line disposed on a substrate; a first pigment layer formed to cover the data line; a second pigment layer disposed by a side of the first pigment layer and formed to have a first region which corresponds to an overlap region of the first and second pigment layers; and common electrodes arranged on second regions in which the first and second pigment layers do not overlap with each other.

Abstract: A switching device includes an opening disposed in a substrate. A source is disposed adjacent the opening and has a contact surface parallel to sidewalls of the opening. A drain is disposed adjacent the opening and has a contact surface parallel to the sidewalls of the opening. A moveable gate stack includes a channel and a gate. The moveable gate stack is disposed within the opening.

Abstract: A bio-sensing semiconductor structure is provided. A transistor includes a channel region and a gate underlying the channel region. A first dielectric layer overlies the transistor. A first opening extends through the first dielectric layer to expose the channel region. A bio-sensing layer lines the first opening and covers an upper surface of the channel region. A second dielectric layer lines the first opening over the bio-sensing layer. A second opening within the first opening extends to the bio-sensing layer, through a region of the second dielectric layer overlying the channel region. A method for manufacturing the bio-sensing semiconductor structure is also provided.

Abstract: The organic electroluminescence display device has a circuit board, an element layer which contains an organic electrode luminescence film and a positive electrode and a negative electrode sandwiching the organic electroluminescence film and which is formed on the circuit board, and a sealing film sealing the element layer. The sealing film contains an inorganic layer covering the element layer and an organic layer formed between a part of the element layer and a part of the inorganic layer. The upper surface of the element layer has an inorganic contact area contacting the inorganic layer and an organic contact area contacting the organic layer. The organic contact area is a hollow in the upper surface of the element layer. The area of the upper surface of the organic layer is smaller than the area of the lower surface contacting the inner surface of the hollow.

Abstract: Semiconductor devices are provided including a first fin-shaped pattern having first and second sidewalls facing one another and a field insulating film contacting at least a portion of the first fin-shaped pattern. The first fin-shaped pattern includes a lower portion of the first fin-shaped pattern contacting the field insulating film; an upper portion of the first fin-shaped pattern not contacting the field insulating film; a first boundary between the lower portion of the first fin-shaped pattern and the upper portion of the first fin-shaped pattern; and a first fin center line perpendicular to the first boundary and meeting the top of the upper portion of the first fin-shaped pattern. The first sidewall of the upper portion of the first fin-shaped pattern and the second sidewall of the upper portion of the first fin-shaped pattern are asymmetric with respect to the first fin center line.

Abstract: A via or pillar structure, and a method of forming, is provided. In an embodiment, a polymer layer is formed having openings exposing portions of an underlying conductive pad. A conductive layer is formed over the polymer layer, filling the openings. The dies are covered with a molding material and a planarization process is performed to form pillars in the openings. In another embodiment, pillars are formed and then a polymer layer is formed over the pillars. The dies are covered with a molding material and a planarization process is performed to expose the pillars. In yet another embodiment, pillars are formed and a molding material is formed directly over the pillars. A planarization process is performed to expose the pillars. In still yet another embodiment, bumps are formed and a molding material is formed directly over the bumps. A planarization process is performed to expose the bumps.

Abstract: A process is provided for contacting a nanostructured surface. In that process, a substrate is provided having a nanostructured material on a surface, the substrate being conductive and the nanostructured material being coated with an insulating material. A portion of the nanostructured material is at least partially removed. A conductor is deposited on the substrate in such a way that it is in electrical contact with the substrate through the area where the nanostructured material has been at least partially removed.

Abstract: A method for forming transistors includes providing a substrate having at least a dummy gate structure having at least dummy gate layer; forming a first dielectric layer on the substrate; thinning the first dielectric layer with a pre-determined depth to cause a top surface of the dielectric layer to be lower than a top surface of the dummy gate structure and expose top portions of side surfaces of the dummy gate structure; forming a stress layer on the exposed portions of the side surfaces of the dummy gate structure; forming a second dielectric layer on the thinned first dielectric layer; removing the dummy gate layer to form an opening with an enlarged top size caused by releasing stress in the stress layer previously formed on the exposed portions of the side surfaces of the dummy gate structure; and forming a gate electrode layer in the opening.

Abstract: A method and structure for receiving a micro device on a receiving substrate are disclosed. A micro device such as a micro LED device is punched-through a passivation layer covering a conductive layer on the receiving substrate, and the passivation layer is hardened. In an embodiment the micro LED device is punched-through a B-staged thermoset material. In an embodiment the micro LED device is punched-through a thermoplastic material.

Abstract: An optoelectronic semiconductor chip includes an interconnection layer with a first electrically conductive contact layer, a second electrically conductive contact layer and an insulation layer, which is formed of an electrically insulating material. Further, the optoelectronic semiconductor chip includes two optoelectronic semiconductor bodies, each of which include an active region that is intended to generate radiation. The insulation layer is arranged on a top of the second electrically conductive contact layer facing the optoelectronic semiconductor bodies. The first electrically conductive contact layer is arranged on a top of the insulation layer remote from the second electrically conductive contact layer. The optoelectronic semiconductor bodies are interconnected electrically in parallel by the interconnection layer.

Abstract: Provided is a method of forming a decoupling capacitor device and the device thereof. The decoupling capacitor device includes a first dielectric layer portion that is deposited in a deposition process that also deposits a second dielectric layer portion for a non-volatile memory cell. Both portions are patterned using a single mask. A system-on-chip (SOC) device is also provided, the SOC include an RRAM cell and a decoupling capacitor situated in a single inter-metal dielectric layer. Also a method for forming a process-compatible decoupling capacitor is provided. The method includes patterning a top electrode layer, an insulating layer, and a bottom electrode layer to form a non-volatile memory element and a decoupling capacitor.

Abstract: A package apparatus comprises a first conductive wiring layer, a first conductive pillar layer, a first conductive glue layer, an internal component, a second conductive pillar layer, a first molding compound layer and a second conductive wiring layer. The first conductive pillar layer is disposed on the first conductive wiring layer. The first conductive glue layer is disposed on the first conductive wiring layer. The internal component has a first electrode layer and a second electrode layer, wherein the first electrode layer is disposed and electrical connected to the first conductive glue layer. The second conductive pillar layer is disposed on the second electrode layer. Wherein the first conductive wiring layer, the first conductive pillar layer, the first conductive glue layer, the internal component and the second conductive pillar layer are disposed inside the first molding compound layer.

Abstract: A hardmask composition may include a solvent and a 2-dimensional carbon nanostructure containing about 0.01 atom % to about 40 atom % of oxygen or a 2-dimensional carbon nanostructure precursor thereof. A content of oxygen in the 2-dimensional carbon nanostructure precursor may be lower than about 0.01 atom % or greater than about 40 atom %. The hardmask composition may be used to form a fine pattern.

Abstract: A method includes epitaxially growing a gallium nitride (GaN) layer over a silicon substrate. The method further includes epitaxially growing a donor-supply layer over the GaN layer. The method further includes forming a source and a drain on the donor-supply layer. The method further includes forming a gate structure between the source and the drain on the donor-supply layer. The method further includes plasma etching a portion of a drift region of the donor-supply layer to a depth of less than 60% of a donor-supply layer thickness. The method further includes depositing a dielectric layer over the donor-supply layer.

Abstract: An organic electro-luminescence display device includes a first substrate, plural pedestals which are provided in a convex shape on the first substrate and have inclined side surfaces, plural first electrodes respectively provided on the respective side surfaces of the pedestals, an organic electro-luminescence film which is provided above the plural pedestals and includes a light-emitting layer laminated on the plural fist electrodes, and a second electrode which is provided above the plural pedestals and is laminated on the organic electro-luminescence film. Light generated in the light-emitting layer is transmitted between a first reflection surface and a second reflection surface. The second electrode includes light transmission parts, through which the light passes, above upper end parts of the pedestals. A surface of the second electrode facing the organic electro-luminescence film is the second reflection surface except for the light transmission parts.

Abstract: A package includes a die, an encapsulant, and a capacitor. The package has a package first side and a package second side. The die has a die first side corresponding to the package first side, and has a die second side corresponding to the package second side. The die first side is opposite the die second side. The encapsulant surrounds the die. The capacitor includes a first plate and a second plate in the encapsulant, and opposing surfaces of the first plate and the second plate extend in a direction from the package first side to the package second side. The external conductive connectors are attached to at least one of the package first side and the package second side.