Abstract: An organic light-emitting diode (OLED) display is disclosed. In one aspect, the display includes a substrate, a switching transistor formed over the substrate, a driving transistor electrically connected to the switching transistor, and a pixel electrode electrically connected to the driving transistor. The display also includes a pixel definition layer covering the pixel electrode and having a pixel opening, an organic emission layer formed only in the pixel opening and connected to the pixel electrode, and a common electrode formed over the organic emission layer. The pixel definition layer is formed over the driving transistor.

Abstract: A semiconductor device includes a substrate including a cell area, a first contact area, and a second contact area; a lower stacked structure extending over the second contact area from the cell area; an upper stacked structure extending over the first contact area from the cell area, the upper stacked structure leaving the second contact area open; N (N is a natural number of 2 or more) first group of stepped grooves penetrating at least one portion of the upper stacked structure in the first contact area; and M (M is a natural number equal to or smaller than N) second group of stepped grooves penetrating at least one portion of the lower stacked structure in the second contact area.

Abstract: A method and structure for receiving a micro device on a receiving substrate are disclosed. A micro device such as a micro LED device is punched-through a passivation layer covering a conductive layer on the receiving substrate, and the passivation layer is hardened. In an embodiment the micro LED device is punched-through a B-staged thermoset material. In an embodiment the micro LED device is punched-through a thermoplastic material.

Abstract: A modification processing method includes preparing a substrate having a silicon layer on which a damage layer is formed through plasma processing. The method further includes removing the damage layer formed on the silicon layer by processing the substrate with a first process gas containing a fluorine gas.

Abstract: The embodiment of the disclosure provides a method for manufacturing a low temperature poly-silicon thin film transistor, comprising forming an interlayer dielectric layer, forming a photoresist layer on the interlayer dielectric layer, and conducting a first photoresist removing on the photoresist layer to expose the interlayer dielectric layer with a first area, etching the interlayer dielectric layer with the first area to form a first depression region, conducting a second photoresist removing on the photoresist layer to expose the interlayer dielectric layer with a second area, and etching the interlayer dielectric layer with the second area and the first depression region to form a second depression region in a step form at the periphery of the first depression region.

Abstract: An acquisition system includes a processor, one or more sensors operatively coupled to the processor where the one or more sensors acquire at the ear, on the ear or within an ear canal, one or more of acceleration, blood oxygen saturation, blood pressure or heart-rate, and the one or more sensors configured to monitor a biological state or a physical motion or both for an event. The event can be a detection of a discrepancy when compared with a set of reference data by the one or more sensors or the biological state or the event can be one of a detection of an abrupt movement of a headset operatively coupled to the processor, a change in location of an earpiece operatively coupled the processor, a touching of the headset, a recognizing of a voice command, a starting or ending of a phone call, or a scheduled time.

Abstract: A method of fabricating a solar cell can include forming a dielectric region on a silicon substrate. The method can also include forming an emitter region over the dielectric region and forming a dopant region on a surface of the silicon substrate. In an embodiment, the method can include heating the silicon substrate at a temperature above 900 degrees Celsius to getter impurities to the emitter region and drive dopants from the dopant region to a portion of the silicon substrate.

Abstract: A flexible multilayer scattering substrate is disclosed. Built on a flexible supporting layer, the multilayer contains one or more scattering layers and other functional layers so that it can extract the trapped light in substrate and waveguide of an OLED. The processing of each layer is fully compatible with large area, flexible OLED manufactory, and by controlling processing conditions of each incorporated layer, the substrate microstructure can be tuned. Topographic features can be created on the top surface of substrate by changing the thickness and properties of the multilayer.

Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within the conductive levels, an insulative material over the stack and a select gate material over the insulative material. An opening extends through the select gate material, through the insulative material, and through the stack of alternating dielectric and conductive levels. A first region of the opening within the insulative material is wider along a cross-section than a second region of the opening within the select gate material, and is wider along the cross-section than a third region of the opening within the stack of alternating dielectric levels and conductive levels. Channel material is within the opening and adjacent the insulative material, the select gate material and the memory cells. Some embodiments include methods of forming vertically-stacked memory cells.

Abstract: There is provided a receiver optical module including a photodetector having a plurality of channels, a capacitor disposing block formed on an upper portion of the photodetector, a plurality of capacitors formed on the capacitor disposing block, and an electrical wiring configured to connect the plurality of capacitors to electrodes of a plurality of channels of the photodetector, wherein the plurality of capacitors are formed on the capacitor disposing block such that distance between the capacitors and the electrodes of the corresponding channels are the same. Distortion and loss of signal characteristics of high frequency can be reduced and quality of a signal can be enhanced.

Abstract: A double-side OLED display is disclosed. The double-side OLED display includes a base layer and an OLED layer disposed on the base layer. The OLED layer includes a first display region and a second display region. The base layer and the OLED layer are folded such that the first display region and the second display region respectively face toward opposite directions; the base layer is located at an outside. The present invention can simplify the production process, increase the production capacity, decrease the thickness of the product, and sufficiently utilizing the base layer such that the base layer can protect the OLED layer. Besides, because the displaying at both sides is emitting at a bottom, the base layer located at outside can provide a flat display surface to improve the display quality.

Abstract: A semiconductor device includes a first fin structure for a first fin field effect transistor (FET). The first fin structure includes a first base layer protruding from a substrate, a first intermediate layer disposed over the first base layer and a first channel layer disposed over the first intermediate layer. The first fin structure further includes a first protective layer made of a material that prevents an underlying layer from oxidation. The first channel layer is made of SiGe, the first intermediate layer includes a first semiconductor (e.g., SiGe) layer disposed over the first base layer and a second semiconductor layer (e.g., Si) disposed over the first semiconductor layer. The first protective layer covers side walls of the first base layer, side walls of the first semiconductor layer and side walls of the second semiconductor layer.

Abstract: Some demonstrative embodiments include devices and/or systems of a Silicon Controlled Rectifier (SCR). For example, a silicon controlled rectifier (SCR) may include a metal-oxide-semiconductor field-effect transistor (MOSFET), the MOSFET may include a gate; an N-type source region; a non-Lightly Doped Drain (LDD) N-type drain region; and a P-Well region extending between the N-type source region and the non-LDD N-type drain region, and extending between the non-LDD N-type drain region and a drain region of the gate.

Abstract: Various embodiments include planar sensor arrays for use in determining characteristics of a material under test (MUT). The planar sensor arrays can include a set of electrodes positioned to enhance a depth and clarity of detection into the material under test. Some embodiments include an electromagnetic sensor array having: a first set of two rectilinear electrodes, positioned opposed to one another across a space; and a second set of two rectilinear electrodes, positioned opposed to one another across the space, the second set being off-set from the first set, wherein the first set and the second set are configured to detect an electromagnetic impedance of the MUT.

Abstract: This invention relates to a flip-chip light-emitting diode and a method for manufacturing the same. The flip-chip light-emitting diode comprises a packaging body and a conductor layer. At least one light-emitting diode chip is encapsulated in the packaging body. The light emitting diode chip has a positive electrode and a negative electrode which are exposed on a side surface of the packaging body. The conductor layer is disposed on the side surface of the packaging body and directly in contact with the positive electrode and the negative electrode of the light-emitting diode chip. The conductor layer has circuit patterns and an insulating portion insulating the positive electrode and the negative electrode of the light-emitting diode chip from each other.

Abstract: A high-voltage MOS transistor includes a semiconductor substrate, a gate oxide layer on the semiconductor substrate, a gate on the gate oxide layer, a spacer covering a sidewall of the gate, a source on one side of the gate, and a drain on the other side of the gate. The gate includes at least a first discrete segment and a second discrete segment. The first discrete segment is not in direct contact with the second discrete segment. The spacer fills into a gap between the first discrete segment and the second discrete segment.

Abstract: A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device includes a first set of through vias between and connecting a top package and a redistribution layer (RDL), the first set of through vias in physical contact with a molding compound and separated from a die. The semiconductor device also includes a first interconnect structure between and connecting the top package and the RDL, the first interconnect structure separated from the die and from the first set of through vias by the molding compound. The first interconnect structure includes a second set of through vias and at least one integrated passive device.

Abstract: Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck having alternating conductor materials and dielectric materials and a hole containing materials extending through the conductor materials and the dielectric materials. The methods can also include forming a sacrificial material in an enlarged portion of the hole and forming a second deck of memory cells over the first deck. Additional apparatuses and methods are described.

Abstract: Semiconductor devices and fin field effect transistors (FinFETs) are disclosed. In some embodiments, a representative semiconductor device includes a group III material over a substrate, the group III material comprising a thickness of about 2 monolayers or less, and a group III-V material over the group III material.

Abstract: The plasma-assisted method of precise alignment and pre-bonding for microstructure of glass and quartz microchip belongs to micromachining and bonding technologies of the microchip. The steps of which are as follows: photoresist and chromium layers on glass or quartz microchip are completely removed followed by sufficient cleaning of the surface with nonionic surfactant and quantities of ultra-pure water. Then the surface treatment is proceeded for an equipping surface with high hydrophily with the usage of plasma cleaning device. Under the drying condition, the precise alignment is accomplished through moving substrate and cover plate after being washed with the help of microscope observation. Further on, to achieve precise alignment and pre-bonding of the microstructure of glass and quartz microchip, a minute quantity of ultrapure water is instilled into a limbic crevice for adhesion, and entire water is completely wiped out by vacuum drying following sufficient squeezing.