Patents Examined by Long K. Tran
  • Fully-depleted SOI MOSFET with U-shaped channel
    Patent number: 9748348
    Abstract: A method of forming a MOSFET device is provided including: providing an SOI wafer; forming a dummy gate oxide and dummy gates on portions of the SOI layer that serve as channel regions of the device; forming spacers and doped source/drain regions in the SOI layer on opposite sides of the dummy gates; depositing a gap fill dielectric; removing the dummy gates/gate oxide; recessing areas of the SOI layer exposed by removal of the dummy gates forming one or more u-shaped grooves that extend part-way through the SOI layer such that a thickness of the SOI layer remaining in the channel regions is less than a thickness of the SOI layer in the doped source/drain regions under the spacers; and forming u-shaped replacement gate stacks in the u-shaped grooves such that u-shaped channels are formed in fully depleted regions of the SOI layer adjacent to the u-shaped replacement gate stacks.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: August 29, 2017
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Robert H. Dennard, Isaac Lauer, Ramachandran Muralidhar
  • Heterojunction semiconductor device having integrated clamping device
    Patent number: 9748224
    Abstract: In one embodiment, a group III-V transistor structure includes a heterostructure disposed on a semiconductor substrate. A first current carrying electrode and a second current carrying electrode are disposed adjacent a major surface of the heterostructure and a control electrode is disposed between the first and second current carrying electrode. A clamping device is integrated with the group III-V transistor structure and is electrically connected to the first current carrying electrode a third electrode to provide a secondary current path during, for example, an electrical stress event.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: August 29, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Balaji Padmanabhan, Prasad Venkatraman, Zia Hossain, Chun-Li Liu, Jason McDonald, Ali Salih, Alexander Young
  • Photo pattern method to increase via etching rate
    Patent number: 9741607
    Abstract: Semiconductor devices are provided having large vias, such as under bonding pads, to increase the via open area ratio, increase the via etching rate, and avoid inter-metal dielectric cracking and damage to the integrated circuit. The via is defined as a large open area in the inter-metal dielectric layer between an isolated conductive bottom substrate layer and a conductive top layer. Methods of manufacturing semiconductor devices with a large via are also provided.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: August 22, 2017
    Assignee: Macronix International Co., Ltd.
    Inventors: Zheng-Chang Mu, Cheng-Wei Lin, Kuang-Wen Liu
  • FinFET device with vertical silicide on recessed source/drain epitaxy regions
    Patent number: 9741807
    Abstract: A method of forming a semiconductor device that includes forming a fin structure from a semiconductor substrate, and forming a gate structure on a channel region portion of the fin structure. A source region and a drain region are formed on a source region portion and a drain region portion of the fin structure on opposing sides of the channel portion of the fin structure. At least one sidewall of the source region portion and the drain region portion of the fin structure is exposed. A metal semiconductor alloy is formed on the at least one sidewall of the source region portion and the drain region portion of the fin structure that is exposed.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: August 22, 2017
    Assignee: International Business Machines Corporation
    Inventors: Keith E. Fogel, Pranita Kerber, Qiqing C. Ouyang, Alexander Reznicek
  • Semiconductor device
    Patent number: 9741725
    Abstract: A semiconductor device can be reduced in size. The semiconductor device has a first conductivity type p type well layer extending in the X direction of the main surface of a semiconductor substrate; a reference potential wire coupled with the p type well layer, and extending in the X direction; first and second active regions arranged on the opposite sides of the reference potential wire in the Y direction; and a gate electrode layer extending in the Y direction in such a manner as to cross with the first and second active regions. Then, the gate electrode layer has a first gate electrode of a second conductivity type at the crossing part with the first active region, a second gate electrode of the second conductivity type at the crossing part with the second active region, and a non-doped electrode between the first gate electrode and the second gate electrode.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: August 22, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Nobuo Tsuboi
  • Chip package and manufacturing method thereof
    Patent number: 9721911
    Abstract: A chip package includes a chip, a laser stopper, an isolation layer, a redistribution layer, an insulating layer, and a conductive structure. The chip has a conductive pad, a first surface, and a second surface. The conductive pad is located on the first surface. The second surface has a first through hole to expose the conductive pad. The laser stopper is located on the conductive pad in the first through hole. The isolation layer is located on the second surface and in the first through hole. The isolation layer has a third surface opposite to the second surface, and has a second through hole to expose the laser stopper. The redistribution layer is located on the third surface, a sidewall of the second through hole, and the laser stopper in the second through hole. The conductive structure is located on the redistribution.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: August 1, 2017
    Assignee: XINTEC INC.
    Inventors: Ho-Yin Yiu, Ying-Nan Wen, Chien-Hung Liu, Shih-Yi Lee
  • Semiconductor device
    Patent number: 9705005
    Abstract: An object of the present invention is to provide a semiconductor device combining transistors integrating on a same substrate transistors including an oxide semiconductor in their channel formation region and transistors including non-oxide semiconductor in their channel formation region. An application of the present invention is to realize substantially non-volatile semiconductor memories which do not require specific erasing operation and do not suffer from damages due to repeated writing operation. Furthermore, the semiconductor device is well adapted to store multivalued data. Manufacturing methods, application circuits and driving/reading methods are explained in details in the description.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: July 11, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Kiyoshi Kato
  • Self-aligned floating gate in a vertical memory structure
    Patent number: 9698022
    Abstract: Methods for building a memory device or electronic system may include a memory cell body extending from a substrate, a self-aligned floating gate separated from the memory cell body by a tunneling dielectric film, and a control gate separated from the self-aligned floating gate by a blocking dielectric film. The floating gate is flanked by the memory cell body and the control gate to form a memory cell, and the self-aligned floating gate is at least as thick as the control gate.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: July 4, 2017
    Assignee: Intel Corporation
    Inventor: Randy J. Koval
  • Semiconductor devices and methods of fabricating the same
    Patent number: 9698155
    Abstract: A semiconductor device includes a plurality of first insulating layers and a plurality of second layers alternately and vertically stacked on a substrate. Each of the plurality of second layers includes a horizontal electrode horizontally separated by a second insulating layer. A contact plug penetrates the plurality of first insulating layers and the second insulating layer of the plurality of second layers.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: July 4, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sunil Shim, Wonseok Cho, Woonkyung Lee
  • Field effect transistor having loop distributed field effect transistor cells
    Patent number: 9698144
    Abstract: A Field Effect Transistor (FET) having a plurality of FET cells having a plurality of source pads, a plurality of drain pads, and a plurality of gate electrodes disposed on a surface of a substrate; each one of the FET cells having a corresponding one of the gate electrodes disposed between one of the source pads and one of the drain pads. The FET includes; a gate contact connected to the gate electrode of each one of the FET cells; a drain contact connected to the drain pad of each one of the FET cells; and a source contact connected to source pad of each one of the FET cells. The cells are disposed in a loop configuration.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: July 4, 2017
    Assignee: Raytheon Company
    Inventors: Istvan Rodriguez, Christopher M. Laighton, Alan J. Bielunis
  • Semiconductor structure having a plurality of conductive paths
    Patent number: 9698099
    Abstract: A semiconductor structure includes a first conductive path and a second conductive path configured to carry a first pair of differential signals representative of an in-phase signal. The semiconductor device further includes a third conductive path and a fourth conductive path configured to carry a second pair of differential signals representative of a quadrature signal corresponding to the in-phase signal. The first and second conductive paths are in a conductive layer of the semiconductor structure, and the third and fourth conductive paths are in another conductive layer of the semiconductor structure.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: July 4, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hui Yu Lee, Feng Wei Kuo, Jui-Feng Kuan, Yi-Kan Cheng
  • Semiconductor device strain relaxation buffer layer
    Patent number: 9698266
    Abstract: A method for forming a semiconductor device comprises forming a first buffer layer with a first melting point on a substrate. A second buffer layer is formed on the first buffer layer. The second buffer layer has a second melting point that is greater than the first melting point. Annealing process is performed that increases a temperature of the first buffer layer such that the first buffer layer partially liquefies and causes a strain in the second buffer layer to be substantially reduced.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: July 4, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Semiconductor device and manufacturing method thereof
    Patent number: 9691903
    Abstract: In a method for manufacturing a semiconductor device, a fin structure including a first semiconductor layer, an oxide layer disposed over the first semiconductor layer and a second semiconductor layer disposed over the oxide layer is formed. An isolation insulating layer is formed so that the second semiconductor layer of the fin structure protrudes from the isolation insulating layer while the oxide layer and the first semiconductor layer are embedded in the isolation insulating layer. A third semiconductor layer is formed on the exposed second semiconductor layer so as to form a channel.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: June 27, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Hsuing Chen, Hou-Yu Chen, Chie-Iuan Lin, Yuan-Shun Chao, Kuo Lung Li
  • Integrated multi-sensor module
    Patent number: 9689824
    Abstract: A semiconductor-based multi-sensor module integrates miniature temperature, pressure, and humidity sensors onto a single substrate. Pressure and humidity sensors can be implemented as capacitive thin film sensors, while the temperature sensor is implemented as a precision miniature Wheatstone bridge. Such multi-sensor modules can be used as building blocks in application-specific integrated circuits (ASICs). Furthermore, the multi-sensor module can be built on top of existing circuitry that can be used to process signals from the sensors. An integrated multi-sensor module that uses differential sensors can measure a variety of localized ambient environmental conditions substantially simultaneously, and with a high level of precision. The multi-sensor module also features an integrated heater that can be used to calibrate or to adjust the sensors, either automatically or as needed.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: June 27, 2017
    Assignee: STMICROELECTRONICS PTE LTD.
    Inventors: Olivier Le Neel, Ravi Shankar, Suman Cherian, Calvin Leung, Tien-Choy Loh, Shian-Yeu Kam
  • Field effect transistor having two-dimensionally distributed field effect transistor cells
    Patent number: 9685438
    Abstract: A Field Effect Transistor (FET) having: a plurality of FET cells having a plurality of source pads, a plurality of drain pads, and a plurality of gate electrodes disposed on a surface of a substrate; each one of the FET cells having a corresponding one of the gate electrodes disposed between one of the source pads and one of the drain pads; a gate contact connected to the gate electrodes of each one of the FET cells; a drain contact connected to the drain pad of each one of the FET cells; and a source contact connected to source pad of each one of the FET cells. The cells are disposed on a surface in a two-dimensional array.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: June 20, 2017
    Assignee: RAYTHEON COMPANY
    Inventors: Christopher M. Laighton, Alan J. Bielunis, Istvan Rodriguez
  • Flexible substrate, flexible display panel and flexible display device
    Patent number: 9685459
    Abstract: The present invention provides a flexible substrate, a flexible display panel and a flexible display device. The flexible substrate includes an on-off element and an insulating layer, wherein a part of the insulating layer serves as a part of the on-off element, and the part of the insulating layer serving as a part of the on-off element is separated from rest part of the insulating layer. In the flexible substrate, the part of the insulating layer serving as a part of the on-off element is separated from the rest part of the insulating layer, such that cracks generated in the reset part of the insulating layer are unlikely to extend to the region where the on-off element is located, thus the poor contact or abnormal on-off phenomenon of the on-off element can be avoided.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: June 20, 2017
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yunfei Li, Ling Shi
  • Semiconductor memory device and method for manufacturing the same
    Patent number: 9685321
    Abstract: A semiconductor memory device in an embodiment includes a semiconductor layer, a control gate electrode, an organic molecular layer provided between the semiconductor layer and the control gate electrode, and a first insulating layer provided between the organic molecular layer and the semiconductor layer, the first insulating layer having a first layer containing alkyl chains and a second layer containing siloxane, the second layer being provided between the first layer and the organic molecular layer.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: June 20, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaya Terai, Shigeki Hattori, Hideyuki Nishizawa, Koji Asakawa
  • Monolithic three-dimensional (3D) ICs with local inter-level interconnects
    Patent number: 9685436
    Abstract: Monolithic 3D ICs employing one or more local inter-level interconnect integrated intimately with at least one structure of at least one transistor on at least one transistor level within the 3D IC. In certain embodiments the local inter-level interconnect intersects a gate electrode or a source/drain region of at least one transistor and extends through at least one inter-level dielectric layer disposed between a first and second transistor level in the 3D IC. Local inter-level interconnects may advantageously make a direct vertical connection between transistors in different levels of the 3D IC without being routed laterally around the footprint (i.e., lateral, or planar, area) of either the overlying or underlying transistor level that is interconnected.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: June 20, 2017
    Assignee: Intel Corporation
    Inventors: Patrick Morrow, Kimin Jun, M. Clair Webb, Donald W. Nelson
  • Methods for manufacturing carbon ribbons for magnetic devices
    Patent number: 9680087
    Abstract: In one embodiment of the invention, there is provided a method for manufacturing a magnetic memory device, comprising: depositing a carbon layer comprising amorphous carbon on a substrate; annealing the carbon layer to activate dopants contained therein; and selectively etching portions of the carbon layer to forms lines of spaced apart carbon conductors.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: June 13, 2017
    Assignee: III HOLDINGS 1, LLC
    Inventor: Krishnakumar Mani
  • Semiconductor device having gate electrode overlapping semiconductor film
    Patent number: 9680026
    Abstract: A semiconductor device that can operate at high speed or having high strength against stress is provided. One embodiment of the present invention is a semiconductor device including a semiconductor film including a channel formation region and a pair of impurity regions between which the channel formation region is positioned; a gate electrode overlapping side and top portions of the channel formation region with an insulating film positioned between the gate electrode and the side and top portions; and a source electrode and a drain electrode in contact with side and top portions of the pair of impurity regions.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: June 13, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki