Abstract: A semiconductor package may include a base layer, and a redistribution layer on the base layer. The semiconductor package may include a first pattern, a second pattern, and a passivation layer covering the first and second patterns. The semiconductor package may include a semiconductor chip on the base layer, a first connection terminal between the base layer and the semiconductor chip and coupled to one of chip pads of the semiconductor chip, and a mold layer between the base layer and the semiconductor chip. The first connection terminal may extend into the passivation layer and may be coupled to the first pattern. The second pattern may be electrically insulated from the semiconductor chip.

Abstract: The present disclosure relates to a mold module that includes a device layer, a number of first bump structures, a first mold compound, a stop layer, and a second mold compound. The device layer includes a number of input/output (I/O) contacts at a top surface of the device layer. Each first bump structure is formed over the device layer and electronically coupled to a corresponding I/O contact. The first mold compound resides over the device layer, and a portion of each first bump structure is exposed through the first mold compound. The stop layer is formed underneath the device layer. The second mold compound resides underneath the stop layer, such that the stop layer separates the device layer from the second mold compound.

Abstract: Semiconductor packages are provided. A semiconductor package includes a substrate including a first bonding region, a chip region, and a second bonding region. Moreover, the substrate includes first and second surfaces that are opposite to each other. The semiconductor package includes a pad group including a pad on the first surface in the chip region. The semiconductor package includes a semiconductor chip on the pad group. The semiconductor package includes a wire connecting the pad and the second bonding region. The wire includes a portion that extends along the second surface of the substrate. Related display devices are also provided.

Abstract: A method for manufacturing a semiconductor device includes forming a conductive pattern on a substrate, forming a filling insulation layer covering the conductive pattern, forming a contact hole in the filling insulation layer and adjacent to the conductive pattern, forming an opening in the conductive pattern by removing a portion of the conductive pattern adjacent to the contact hole such that the opening is connected to the contact hole, and forming a contact plug filling the contact hole and the opening. A width of the opening is greater than a width of the contact hole.

Abstract: Embodiments of three-dimensional (3D) memory devices having multiple memory stacks and methods for forming the 3D memory devices are disclosed. In an example, a 3D memory device includes a first device chip, a second device chip, and a bonding interface. The first device chip includes a peripheral device and a first interconnect layer. The second device chip includes a substrate, two memory stacks disposed on opposite sides of the substrate, two memory strings each extending vertically through one of the two memory stacks, and a second interconnect layer. The bonding interface is formed vertically between the first interconnect layer of the first device chip and the second interconnect layer of the second device chip.

Abstract: An electronic package and a method for fabricating the same are provided. The method includes disposing on a carrier an electronic component having a plurality of conductors, encapsulating the electronic component with an encapsulant, and disposing an electronic device on the encapsulant. The electronic device and the carrier are electrically connected through the conductors, thereby reducing the overall thickness of the electronic package.

Abstract: A multi-device package includes a substrate, at least two device regions, a first redistribution layer, an external chip and a plurality of first connectors. The two device regions are formed from the substrate, and the first redistribution layer is disposed on the substrate and electrically connected to the two device regions. The external chip is disposed on the first redistribution layer, and the first connectors are interposed between the first redistribution layer and the external chip to interconnect the two.

Abstract: A three-dimensional stacking technique performed in a wafer-to-wafer fashion reducing the machine movement in production. The Wafers are processed with metallic traces and stacked before dicing into separate die stacks. The traces of each layer of the stacks are interconnected via electroless plating.

Abstract: The present disclosure relates to a mold module that includes a device layer, a number of first bump structures, a first mold compound, a stop layer, and a second mold compound. The device layer includes a number of input/output (I/O) contacts at a top surface of the device layer. Each first bump structure is formed over the device layer and electronically coupled to a corresponding I/O contact. The first mold compound resides over the device layer, and a portion of each first bump structure is exposed through the first mold compound. The stop layer is formed underneath the device layer. The second mold compound resides underneath the stop layer, such that the stop layer separates the device layer from the second mold compound.

Abstract: Examples disclosed herein involve integrated circuit chip arrangements. An example integrated circuit (IC) package may include a first semiconductor chip that includes a first metal-oxide-semiconductor field-effect transistor (MOSFET) and a second semiconductor chip mounted within a housing of the IC package. The second semiconductor chip may include a second MOSFET and a control circuit configured with a first driver for the first MOSFET and a second driver for the second MOSFET. The first semiconductor chip may be mounted to the second semiconductor chip opposite a base of the IC package.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate, a die and a seal ring. The die is configured to be in and on the semiconductor substrate. The seal ring is configured to be on the semiconductor substrate and adjacent to the die. The seal ring forms an open loop.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate, a dielectric layer, and silicide layer. The semiconductor substrate has a plurality of protrusions. The dielectric layer is disposed over the semiconductor substrate and has a plurality of blocks disposed over the protrusions. The silicide layer is disposed over a first sidewall of the protrusions, a second sidewall of the blocks, and an upper surface of the semiconductor substrate adjacent to the first sidewall, and a bottom surface of the silicide layer is lower than a first surface of the semiconductor substrate. The present disclosure further provides a method for manufacturing the semiconductor structure.

Abstract: A semiconductor device can include a plurality of landing pads arranged according to a layout on a substrate, wherein a cross-sectional shape of each of the landing pads has a diamond shape so that opposing interior angles of the diamond shape are equal to one another and adjacent interior angles of the diamond shape are unequal to one another.

Abstract: Wireless modules having a semiconductor package attached to an antenna package is disclosed. The semiconductor package may house one or more electronic components as a single die package and/or a system in a package (SiP) implementation. The antenna package may be communicatively coupled to the semiconductor package using by one or more coupling pads. The antenna package may further have one or more radiating elements for transmitting and or receiving wireless signals. The antenna package and the semiconductor package may have dissimilar number of interconnect layers and/or dissimilar materials of construct.

Abstract: An embedded silicon substrate fan-out type 3D packaging structure, comprising: a silicon substrate; and at least one functional chip, wherein the silicon substrate includes at least one groove, the at least one functional chip is embedded in the at least one groove with a pad surface facing upward, the at least one functional chip is bonded with the at least one groove through a polymer; a front surface of the silicon substrate, the pad surface of the at least one functional chip, and at least one gap between the at least one chip and the at least one groove are covered with a polymer material, and the polymer on pads on the at least one functional chip is opened; at least one conductive through hole is formed on the silicon substrate; and the silicon substrate further includes electrical interconnect structures, a first metal re-wiring and a second metal re-wiring.

Abstract: An object of the present invention is to provide an anisotropic conductive bonding member capable of achieving excellent conduction reliability and insulation reliability, a semiconductor device using the same, a semiconductor package, and a semiconductor device production method. An anisotropic conductive bonding member of the present invention includes an insulating base which is made of an inorganic material, a plurality of conductive paths which are made of a conductive member, penetrate the insulating base in a thickness direction thereof, and are provided in a mutually insulated state, and a pressure sensitive adhesive layer which is provided on a surface of the insulating base, in which each of the conductive paths has a protrusion protruding from the surface of the insulating base, the protrusion of each of the conductive paths is buried in the pressure sensitive adhesive layer, and the pressure sensitive adhesive layer contains a polymer material and an antioxidant material.

Abstract: An electronic device includes a top carrier having a first top surface and a first bottom surface, a first electronic element formed on the first top surface, a second electronic element formed on the first bottom surface, a bottom carrier below the top carrier and having a second top surface near the top carrier, and a controller formed on the second top surface.

Abstract: A semiconductor wafer is provided. The semiconductor wafer includes a wafer body including a first surface and a second surface opposite the first surface; and a bevel portion disposed along an outer circumference of the wafer body and including an inclined surface, an outermost point, a first surface end portion connecting the bevel portion to the first surface and a second surface end portion connecting the bevel portion to the second surface. A first bevel angle between a first tangential direction of the inclined surface and the first surface corresponds to a capillary force of a fluid on the first surface, and a first bevel length between the first surface end portion and the outermost point along a first direction substantially parallel to the first surface corresponds to a first surface flatness.

Abstract: A plurality of interconnect features are formed in an interconnect layer on a first insulating layer on a substrate. An opening in the first insulating layer is formed through at least one of the interconnect features. A gap fill layer is deposited in the opening.

Abstract: A liner-free or partial liner-free contact/via structure that is embedded within a dielectric capping layer and positioned between an electrically conductive structure and an overlying contact structure is provided.