Abstract: A semiconductor package and a manufacturing method are provided. The semiconductor package includes a die, a dummy cube, a stress relaxation layer, an encapsulant and a redistribution structure. The dummy cube is disposed beside the die. The stress relaxation layer covers a top surface of the dummy cube. The encapsulant encapsulates the die and the dummy cube. The redistribution structure is disposed over the encapsulant and is electrically connected to the die. The stress relaxation layer is interposed between the dummy cube and the redistribution structure.

Abstract: Described examples include a device including a semiconductor die having a first surface with bond pads and an opposite second surface attached to a substrate by an adhesive layer covering at least a portion of the surface area of the second surface. The adhesive layer includes first zones composed of a first polymeric compound and adding up to a first portion of the surface area, and second zones composed of a second polymeric compound and adding up to a second portion of the surface area, the first zones and the second zones being contiguous. The first polymeric compound has a first modulus and the second polymeric compound has a second modulus greater than the first modulus.

Abstract: Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a substrate, a first device layer disposed on the substrate, and a first bonding layer disposed above the first device layer and including a first bonding contact. The second semiconductor structure includes a second device layer and a second bonding layer disposed below the second device layer and including a second bonding contact. The first bonding contact is in contact with the second bonding contact at the bonding interface. At least one of the first bonding contact or the second bonding contact is made of an indiffusible conductive material.

Abstract: Wafer level package structures and packaging methods are provided. An exemplary method includes providing a device wafer having a first front surface and a first back surface opposing the first front surface, wherein at least one first chip is integrated in the first front surface; forming a first oxide layer on the first front surface of the device wafer; providing at least one second chip having a to-be-bonded surface; forming a second oxide layer on the to-be-bonded surface of each second chip; providing a carrier wafer; temporally bonding a surface of the second chip opposing the second oxide layer to the carrier wafer; forming an encapsulation layer on the carrier wafer between adjacent second chips of the at least one second; and bonding the device wafer and the second chip by bonding the first oxide layer with the second oxide layer by a low-temperature fusion bonding process.

Abstract: The present disclosure provides a fan-out antenna packaging structure and a preparation method thereof. The fan-out antenna packaging structure comprises: a semiconductor chip; a plastic packaging material layer enclosing a periphery of the semiconductor chip, a via being formed in the plastic packaging material layer; a conductive pole located in the via and running through the plastic packaging material layer from top to bottom; an antenna structure located on a first surface of the plastic packaging material layer and electrically connected with the conductive pole; a redistribution layer located on a second surface of the plastic packaging material layer and electrically connected with the semiconductor chip and the conductive pole; and a solder bump located on a surface of the redistribution layer, electrically connected with the redistribution layer and insulated from the plastic packaging material layer.

Abstract: Provided is a semiconductor device having: a terminal portion having a through hole is formed on a principal surface portion; and a casing portion in which an opening to make the principal surface portion of the terminal portion exposed is provided, wherein the opening has a corner portion corresponding to a corner of the principal surface portion of the terminal portion, wherein the casing portion has a thick portion, in which thickness of a resin may be greater than that of a middle portion between adjacent corner portions across two sides forming the corner portion, in a surrounding area of the opening. Furthermore, a slit portion extending outward from the corner portion may be formed in the casing portion. At least a part of the outline of the slit portion as viewed from the upper surface direction of the casing portion may be curved.

Abstract: A chip packaging structure and method, and an electronic device, are provided. The chip packaging structure includes a support, a chip, at least one conductor, and a package for plastic packaging the support, the chip and the conductor. The chip is arranged on an upper surface of the support, a chip pad is formed on the upper surface of the chip, and the chip pad is connected to an external pad of the support by a bonding wire. The conductor is connected to the external pad or a ground pad of the chip pad, and the shortest distance from the conductor to the upper surface of the package is less than the shortest distance from the bonding wire to the upper surface of the package, whereby chip failure caused by static electricity discharge is greatly reduced.

Abstract: An electrical joint structure including a substrate, a multi-layer bonding structure, and a blocking layer is provided. The multi-layer bonding structure is present on the substrate and includes a diffusive metal layer and a tin-rich layer. The diffusive metal layer includes a copper-tin alloy on a surface of the diffusive metal layer. The surface faces the substrate. A thickness of the copper-tin alloy is less than or equal to 2 ?m. The tin-rich layer is present on and in contact with the diffusive metal layer. The blocking layer is present between the multi-layer bonding structure and the substrate and at least in contact with a part of said copper-tin alloy, such that the multi-layer bonding structure is spaced apart from the substrate.

Abstract: The present disclosure relates to a mold module that includes a device layer, a number of first bump structures, a first mold compound, a stop layer, and a second mold compound. The device layer includes a number of input/output (I/O) contacts at a top surface of the device layer. Each first bump structure is formed over the device layer and electronically coupled to a corresponding I/O contact. The first mold compound resides over the device layer, and a portion of each first bump structure is exposed through the first mold compound. The stop layer is formed underneath the device layer. The second mold compound resides underneath the stop layer, such that the stop layer separates the device layer from the second mold compound.

Abstract: The present disclosure provides a packaging method for wafer-level system in package. The packaging method for wafer-level system in package includes bonding at least two wafers together along a stacking direction perpendicular to surfaces of the at least two wafers, each wafer containing a plurality of chips. The bonding includes adjoining two wafers to-be-bonded together, and after adjoining, forming a plurality of plugs to electrically connect the plurality of chips in the two wafers.

Abstract: The present disclosure provides a wafer-level packaging method and a package structure. The wafer-level packaging method includes: providing a device wafer that contains a plurality of first chips, that each first chip contains a first electrode exposed at a wafer front surface of the device wafer; providing a plurality of second chips, that each second chip contains a second electrode exposed at a chip front surface of the each second chip, and a surface opposite to the chip front surface is a chip back surface; bonding the chip back surface of the each second chip to a portion of the wafer front surface of the device wafer between adjacent first chips of the plurality of first chips; forming insulating sidewalls on sidewalls of the plurality of second chips; and forming a conductive layer conformally covering the chip front surface, each insulating sidewall, and the wafer front surface.

Abstract: Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.

Abstract: Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first and a second semiconductor structures. The first semiconductor structure includes a first interconnect layer including first interconnects. At least one first interconnect is a first dummy interconnect. The first semiconductor structure further includes a first bonding layer including first bonding contacts. Each first interconnect is in contact with a respective first bonding contact. The second semiconductor structure includes a second interconnect layer including second interconnects. At least one second interconnect is a second dummy interconnect. The second semiconductor structure further includes a second bonding layer including second bonding contacts. Each second interconnect is in contact with a respective second bonding contact. The semiconductor device further includes a bonding interface between the first and second bonding layers.

Abstract: A method includes forming a polymer layer covering a metal via in a wafer, grooving the wafer to form a trench, wherein the trench extends from a top surface of the polymer layer into the wafer, and performing a die-saw on the wafer to separate the wafer into a plurality of device dies. A kerf passes through the trench. One of the device dies is placed over a carrier. An encapsulating material is dispensed over and around the device die. The method further includes pressing and curing the encapsulating material. After the encapsulating material is cured, a sidewall of the polymer layer is tilted. A planarization is performed on the encapsulating material until the polymer layer and the metal via are exposed. A redistribution line is formed over and electrically coupled to the metal via.

Abstract: A method of manufacturing a semiconductor power package includes: embedding a power semiconductor chip in an encapsulation, the encapsulation forming a housing of the semiconductor power package; and extending a layer of a covering material over at least a part of an outer main surface of the encapsulation. The covering material has a thermal conductivity greater than a thermal conductivity of the material of the encapsulation and/or a temperature stability greater than a temperature stability of the pre-molded chip housing.

Abstract: A method for forming a semiconductor structure including forming a plurality of mandrel lines on a first dielectric layer and forming one or more groups of discontinuous mandrel line pairs with a first mask. The method further includes disposing a second dielectric layer, and forming dielectric spacers on sidewalls of the mandrel lines and the discontinuous mandrel line pairs. The method further includes removing the mandrel lines and the discontinuous mandrel line pairs to form spacer masks, forming one or more groups of blocked regions using a second mask, and forming openings extended through the first dielectric layer with a conjunction of the spacer masks and the second mask. The method also includes removing the spacer masks and the second mask, disposing an objective material in the openings, and forming objective lines with top surfaces coplanar with the top surfaces of the first dielectric layer.

Abstract: A chip packaging structure comprises a die, a carrier, a die attach film, and a plastic package body. The die attach film is disposed on the bottom surface of the die, with a thickness of the die attach film being greater than or equal to 40 micrometers. The die is disposed on the carrier via the die attach film; and the plastic package body is disposed on the carrier and coats a top surface and side surfaces of the die, whereby the overall impact resistance of a chip is improved without changing the structure of the carrier, the expense for making a mold is saved, and moreover, the packaging structure is simple and easy for mass production.

Abstract: A wafer level package which includes an IC chip; a rewiring layer on the IC chip; and a capacitor embedded in the rewiring layer.

Abstract: An ESD protection device for protecting an integrated circuit against an ESD event includes a first terminal coupled to an input/output pad of the IC, a second terminal coupled to a reference or ground voltage, a silicon-controlled rectifier device having an anode connected to the first terminal and a cathode connected to the reference or ground voltage, and a pnp transistor coupled in parallel with the SCR device. The pnp transistor has an emitter coupled to the first terminal, a collector coupled to the second terminal, and a base coupled to a gate of the SCR. The pnp transistor includes a contact region formed at a first side of a substrate, the first contact region being surrounded by an STI layer formed at the first side of the substrate. An insulation structure is formed at an intersection of the first contact region and the STI layer.

Abstract: Present disclosure provides a semiconductor structure, including a semiconductor substrate having an active side, an interconnect layer in proximity to the active side of the semiconductor substrate, and a through substrate via extending from the semiconductor substrate to a first metal layer of the interconnect layer. The TSV being wider than the continuous metal feature. Present disclosure also provides a method for manufacturing the semiconductor structure described herein.