Abstract: A method to construct a 3D system, the method including: providing a base wafer; and then transferring a first memory wafer on top of the base wafer; and then thinning the first memory wafer; and then transferring a second memory wafer on top of the first memory wafer; and then thinning the second memory wafer; and transferring a memory control on top of the second memory wafer; and then thinning the memory control, where the first memory wafer includes a cut-layer, and where the thinning of the first memory wafer includes using the cut-layer to control the thickness of the first memory wafer.

Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, the electrical package may include a first package layer. A plurality of signal lines with a first thickness may be formed on the first package layer. Additionally, a power plane with a second thickness may be formed on the first package layer. According to an embodiment, the second thickness is greater than the first thickness. Embodiments of the invention may form the power plane with a lithographic patterning and deposition process that is different than the lithographic patterning and deposition process used to form the plurality of signal lines. In an embodiment, the power plane may be formed concurrently with vias that electrically couple the signal lines to the next routing layer.

Abstract: A case includes a terminal disposition portion which includes a disposition surface projecting from an inner wall surface toward an open area, exposes an exposure region on a front surface of an external connecting terminal, and embeds therein a rear surface of the external connecting terminal. In the case, at at least part of both sides along a pair of opposite sides of the exposure region, the disposition surface is located between the front surface and the rear surface to have a level difference to the front surface. In a semiconductor device with the above-described configuration, the case does not extend to the exposure region on the front surface of the external connecting terminal. Therefore, no encapsulation resin flows into an interfacial debonding gap between the external connecting terminal and the case, thus curbing further advance of the interfacial debonding.

Abstract: A plasma polymerized thin film having low dielectric constant prepared by depositing a first precursor material represented by the following Chemical Formula 1: wherein in the above Chemical Formula 1, R1 to R14 are each independently H or a substituted or non-substituted C1-C5 alkyl group, and when the R1 to R14 are substituted, their substituents comprise an amino group, a hydroxyl group, a cyano group, a halogen group, a nitro group, or a methoxy group.

Abstract: Insulating layers of a redistribution layer of a semiconductor package may be formed as a polymer film having inorganic fillers formed therein. The inorganic fillers may trap reactive materials to inhibit and/or substantially prevent the metal conductors, such as chip pads of the semiconductor chip being packaged, from being damaged by the reactive material. As a result, the reliability and the durability of the semiconductor package may be improved.

Abstract: A semiconductor device package and a method of manufacturing the same are provided. The semiconductor device package includes a circuit layer, a first package body, a first antenna and an electronic component. The circuit layer has a first surface and a second surface opposite to the first surface. The first package body is disposed on the first surface of the circuit layer. The first antenna penetrates the first package body and is electrically connected to the circuit layer. The electronic component is disposed on the second surface of the circuit layer.

Abstract: Disclosed herein are apparatuses and methods for configuring a circuit board to have a plurality of die having different bottom-side electrical potential. An apparatus comprises a circuit board comprising a metallic base plate, a thermally conductive dielectric, and a plurality of metallic pads. Each of a plurality of die of the apparatus is coupled to a respective one of the plurality of metallic pads, and the plurality of die comprises a first die and a second die. Based on each of the plurality of die being coupled to a respective one of the plurality of metallic foil pads, the first die is configured to exhibit a first bottom-side electrical potential and the second die is configured to exhibit a second bottom-side electrical potential. The apparatus is further configured to conduct heat from the plurality of die away from the plurality of die via at least the metallic base plate, the thermally conductive dielectric, and the plurality of metallic pads.

Abstract: A substrate of the present invention sequentially includes an insulating substrate, a lower layer, a first insulating film, a second insulating film, and an upper layer. The substrate is provided with a hole reaching at least one of the lower layer or the insulating substrate through at least the first insulating film and the second insulating film. The first insulating film includes in a region with the hole a protrusion that protrudes from an end portion in contact with the first insulating film of the second insulating film. The substrate includes a stepwise structure including the protrusion and the end portion. The upper layer coats the stepwise structure. An upper surface portion of the first insulating film in a region with the protrusion and an upper surface portion of the first insulating film in a region below the end portion of the second insulating film are coplanar.

Abstract: A method includes forming a first polymer layer to cover a metal pad of a wafer, and patterning the first polymer layer to form a first opening. A first sidewall of the first polymer layer exposed to the first opening has a first tilt angle where the first sidewall is in contact with the metal pad. The method further includes forming a metal pillar in the first opening, sawing the wafer to generate a device die, encapsulating the device die in an encapsulating material, performing a planarization to reveal the metal pillar, forming a second polymer layer over the encapsulating material and the device die, and patterning the second polymer layer to form a second opening. The metal pillar is exposed through the second opening. A second sidewall of the second polymer layer exposed to the second opening has a second tilt angle greater than the first tilt angle.

Abstract: The present application relates to an optical filter and an organic light-emitting display device. The optical filter of the present application has excellent omnidirectional antireflection performance on the side as well as the front. The optical filter can be applied to an organic light-emitting device to improve visibility.

Abstract: A semiconductor package structure includes an interconnection structure having a first surface and a second surface opposite to the first surface, a die surrounded by a molding compound over the first surface of the interconnection structure, and a passive device surrounded by a dielectric structure over the second surface of the interconnection structure. The passive device is electrically coupled to the die by the interconnection structure.

Abstract: An integrated fan-out package includes a die, an insulating encapsulation, a redistribution circuit structure, conductive terminals, and barrier layers. The insulating encapsulation encapsulates the die. The redistribution circuit structure includes a first redistribution conductive layer on the insulating encapsulation, a first inter-dielectric layer covering the first redistribution conductive layer, and a second redistribution conductive layer on the first inter-dielectric layer. The first redistribution conductive layer includes conductive through vias extending from a first surface of the insulating encapsulation to a second surface of the insulating encapsulation. The first inter-dielectric layer includes contact openings, portions of the second redistribution conductive layer filled in the contact openings are in contact with the first redistribution conductive layer and offset from the conductive through vias.

Abstract: Systems and methods for maskless gap (for example, air gap) integration into multilayer interconnects having one or more interconnect lines (for example, metal interconnect lines) embedded in a dielectric layer of the interconnects are described. In various embodiments, the described systems and methods may serve to reduce electrical shorting between adjacent vias in the interconnects. In one embodiment, a spacer layer may be provided to mask portions of an interlayer dielectric (ILD) in the interconnect. These masked portions of the ILD can protect regions between adjacent interconnect lines (for example, metal interconnect lines) from electrical shorting during subsequent metal layer depositions, for example, during a fabrication sequence of the interconnects. Further, the vias may enclose a gap (for example, an air gap) without the need for additional masking steps. Further, such gaps may be inherently self-aligned to the vias and/or spacer layers.

Abstract: Methods for forming semiconductor structures are disclosed, including a method that involves forming sets of conductive material and insulating material, forming a first mask over the sets, forming a first number of contact regions, forming a second mask over a first region of the sets, and removing material from the sets in a second, exposed region laterally adjacent the first region to form a second number of contact regions. Another method includes forming first and second contact regions on portions of sets of conductive materials and insulating materials, each of the second contact regions more proximal to an underlying substrate than each of the first contact regions. Apparatuses such as memory devices including laterally adjacent first and second regions each of which including contact regions of a different portion of a plurality of conductive materials and related methods of forming such devices are also disclosed.

Abstract: A housing for accommodating an electronic component of an electronic assembly includes a base and a cover, wherein the base and the cover are connected to one another by a hinge element and the base and the cover of the housing can be folded together by means of the hinge element. At least one leadframe has conductor tracks arranged in the housing, wherein at least one conductor track of the leadframe is arranged in the base of the housing and at least one further conductor track is arranged in the cover of the housing, and wherein the at least one further conductor track extends starting from the base of the housing, via the hinge element, to the cover of the housing.

Abstract: An apparatus including a circuit structure including a device stratum; and a contact coupled to a supply line and routed through the device stratum and coupled to at least one device on a first side. A method including providing a supply from a package substrate to at least one transistor in a device stratum of a circuit structure; and distributing the supply to the at least one transistor using a supply line on an underside of the device stratum and contacting the at least one transistor on a device side by routing a contact from the supply line through the device stratum. A system including a package substrate, and a die including at least one supply line disposed on an underside of a device stratum and routed through the device stratum and coupled to at least one of a plurality of transistor devices on the device side.

Abstract: The field-effect mobility and reliability of a transistor including an oxide semiconductor film are improved. A semiconductor layer of a transistor is formed using a composite oxide semiconductor in which a first region and a second region are mixed. The first region includes a plurality of first clusters containing one or more of indium, zinc, and oxygen as a main component. The second region includes a plurality of second clusters containing one or more of indium, an element M (M represents Al, Ga, Y, or Sn), zinc, and oxygen. The first region includes a portion in which the plurality of first clusters are connected to each other. The second region includes a portion in which the plurality of second clusters are connected to each other.

Abstract: Certain aspects of the present disclosure generally relate to a chip package having a split conductive pad for coupling to a device terminal. An example chip package generally includes a layer, a first plurality of conductive pads disposed on the layer, at least one conductive trace disposed on the layer and between the first plurality of conductive pads, and an electrical component having a first terminal coupled to the first plurality of conductive pads and disposed above the at least one conductive trace.

Abstract: A display device includes a substrate including pixel electrodes, a first data line extending in the first direction and through which a data signal is supplied to the pixel electrodes in a first region that is close to one ends of the pixel electrodes in the first direction, and a second data line extending in the first direction and through which a data signal is supplied to the pixel electrodes in a second region that is closer to another ends of the pixel electrodes in the first direction than the first region is, and a driver circuit disposed close to the one ends of the pixel electrodes and configured to supply a data signal to each of the pixel electrodes through the first data line and the second data line. The first data line and the second data line are overlapped with each other in the first region.

Abstract: The present invention provides a semiconductor structure and a method of fabricating the same. The method includes: providing a chip having conductive pads, forming a metal layer on the conductive pads, forming a passivation layer on a portion of the metal layer, and forming conductive pillars on the metal layer. Since the metal layer is protected by the passivation layer, the undercut problem is solved, the supporting strength of the conductive pillars is increased, and the product reliability is improved.