Patents Examined by Lucien U. Toplu
  • Patent number: 6732138
    Abstract: A method and system are disclosed for managing access to system resources by a user process within a multitasking data processing system. The data processing system includes a processor for executing kernel threads scheduled to the processor and a memory having a user address space which stores an application program and a kernel address space which stores an operating system kernel. The operating system kernel includes a kernel process comprising one or more first kernel threads which can each access the system resources. The user address space also stores a user process which has ownership of the system resources. The user process includes a second kernel thread comprising instructions within the application program. To access certain system resources, the second kernel thread invokes a first kernel thread within the user process.
    Type: Grant
    Filed: July 26, 1995
    Date of Patent: May 4, 2004
    Assignee: International Business Machines Corporation
    Inventors: Luke Matthew Browning, Jeffrey Scot Peek
  • Patent number: 6234689
    Abstract: The present invention is a method for accessing a user defined custom routine through a graphical interface of an application program. The method comprises the steps of: (a) linking the user defined custom routine to the application program; (b) displaying a means for accessing the user defined custom routine on a graphical interface; and (c) transferring control to the user defined custom routine when a user activates the means.
    Type: Grant
    Filed: November 14, 1995
    Date of Patent: May 22, 2001
    Assignee: Hewlett-Packard Co.
    Inventors: John G. Rohrbaugh, Thomas H. Baker, Michael J. Bennett, Mercedes E. Gil, Robert W. Proulx
  • Patent number: 6151637
    Abstract: A computer implemented transaction processing system is presented for processing transactions between an application and one or more transaction processors. The system utilizes a first communication link between the application and a transaction processor interoperability component. Then, the system determines which of the one or more transaction processors will process transactions for the application and establishes a communication link between the transaction processor interoperability component and the transaction processor that will process transactions for the application.
    Type: Grant
    Filed: September 4, 1996
    Date of Patent: November 21, 2000
    Assignee: Insession, Inc.
    Inventors: Mark Phillips, Michael Blevins
  • Patent number: 6138168
    Abstract: Provided are a system and method for supporting communication between application programs and the processing of messages by those programs. A table driven approach is used to select appropriate components of modular application programs to process received messages. The selection is carried out in dependence on associations between message types (e.g. request, inform, reply) and other characteristics of the message (e.g. whether the message is an expected reply (as identified by an identifier value). Also used in said selection are dynamic characteristics of the message or the system (e.g. possibly expiry of a timeout, or the state of an application). Rules combine these criteria and determine the conditions for invoking an application program component.Also provided is a mechanism for differentiating between reply messages which are received out of serial sequence but are still current and messages which are invalid.
    Type: Grant
    Filed: September 10, 1996
    Date of Patent: October 24, 2000
    Assignee: International Business Machines Corporation
    Inventors: John Anthony Kelly, Ian Michael McCallion
  • Patent number: 6108684
    Abstract: Methods and associated apparatus for balancing the I/O request processing load within a plurality of controllers in a storage subsystem. The methods of the present invention are operable within interconnected controllers of a storage subsystem to shift the processing of received I/O requests to less loaded controllers and to do so in a manner transparent to legacy attached host systems. In a first embodiment of the present invention referred to as back-end load balancing, I/O requests are transferred from a first controller, to which the I/O request was directed by the attached host system, to a second controller for further processing. In this back-end load balancing embodiment, all write data associated with a write request as well as returned information including status or read data, is exchanged between the first and second controllers such that the first controller performs all communication with the attached host system.
    Type: Grant
    Filed: December 23, 1996
    Date of Patent: August 22, 2000
    Assignee: LSI Logic Corporation
    Inventors: Rodney A. DeKoning, Gerald J. Fredin, Charles D. Binford
  • Patent number: 6108683
    Abstract: A computer-system fixed-priority process scheduler that is supported by an operating system (OS) and establishes fixed priorities respectively corresponding to a plurality of processes to be scheduled. Further, the priorities can be changed by designation from the user processes. The process scheduler allocates a central processing unit (CPU) to executable ones of the processes in the descending order of the priorities thereof. Moreover, a user-level process scheduler is provided in a fixed-priority process scheduler space, namely, in a real-time class process scheduler space. The user-level process scheduler has a first priority of a real time class. Furthermore, the user-level process scheduler performs the scheduling of a group of other user processes, which have priorities lower than the first priority, and causes the group of such user processes to operate or run.
    Type: Grant
    Filed: March 21, 1996
    Date of Patent: August 22, 2000
    Assignee: Fujitsu Limited
    Inventors: Jun Kamada, Masanobu Yuhara, Etsuo Ono
  • Patent number: 6101525
    Abstract: A shared memory clean application system assigns a process name to each process operating within a shared memory region and stores that name in shared memory elements used by that process. If there are more processes sharing an element than that element has space to keep the names, an overflow element is created and linked to the shared element. When a new element is requested and no free elements are available, the invention selects an element, clears its use count, and then reviews all the names in that shared element array to see if they match existing valid processes. If an existing process is found that matches a name in the array, the use count is incremented for that process. If no existing process match is found for a process name in the element array, that name is deleted from the array. If overflow elements exist, they are also cleared of names that do not match, or deallocated entirely if the review indicates there is an overflow element that no longer has process names associated with it.
    Type: Grant
    Filed: May 19, 1995
    Date of Patent: August 8, 2000
    Assignee: EMC Corporation
    Inventor: Mark Bennett Hecker
  • Patent number: 6075940
    Abstract: The present invention provides a verifier for use in conjunction with programs utilizing data type specific bytecodes for verifying the proper operation of the executable program prior to actual execution by a host processor. A verifier is provided which includes a virtual stack for temporarily storing stack information which parallels the typical stack operations required during the execution a bytecode program. The verifier also includes a stack snapshot storage structure having a snapshot directory and stack snapshot storage area for storing the state of the virtual stack at various points during program verification so as to assure proper stack manipulations by the source program. A two step source program verification process is provided for in which the source program is initially loaded into the verifier and a first pass source program evaluation is performed.
    Type: Grant
    Filed: May 19, 1997
    Date of Patent: June 13, 2000
    Assignee: Sun Microsystems Inc.
    Inventor: James A. Gosling
  • Patent number: 6067575
    Abstract: A distributed computer system has a program compiling computer and a program executing computer. The program compiling computer is operated by a compiling party and includes a compiler that, when the digital signature of the originating party of an architecture neutral program has been verified, (A) compiles the architecture neutral program code of the architecture neutral program into architecture specific program code in the architecture specific language identified by the compile to information in the architecture neutral program, and (B) appends to the architecture specific program code a digital signature of the compiling party to generate an architecture specific program.
    Type: Grant
    Filed: December 8, 1995
    Date of Patent: May 23, 2000
    Assignee: Sun Microsystems, Inc.
    Inventors: Charles E. McManis, Frank Yellin
  • Patent number: 6065037
    Abstract: This is achieved in a computer system employing a multiple facility operating system architecture. The computer system includes a plurality of processor units for implementing a predetermined set of peer-level facilities wherein each peer-level facility includes a plurality of related functions and a communications bus for interconnecting the processor units. Each of the processor units includes a central processor and the stored program that, upon execution, provides for the implementation of a predetermined peer-level facility of the predetermined set of peer-level facilities, and for performing a multi-tasking interface function. The multi-tasking interface function is responsive to control messages for selecting for execution functions of the predetermined peer-level facility and that is responsive to the predetermined peer-level facility for providing control messages to request or to respond to the performance of functions of another peer-level facility of the computer system.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: May 16, 2000
    Assignee: Auspex Systems, Inc.
    Inventors: David Hitz, Allan Schwartz, James Lau, Guy Harris
  • Patent number: 6055558
    Abstract: A system and method for pacing, or controlling, the processing of multiple producers when a consumer requires results from the producers in natural order. This invention regulates the use of system resources between the producers to ensure that the required results are available to the consumer in natural order with minimal waiting and to prevent unneeded advanced processing by the producers. This invention implements a buffer structure such that each producer writes its results to an associated buffer. Each producer compares its buffer's percentage complete against a next and previous producer's buffer. If a producer produces results too rapidly, the producer suspends itself until it is resumed by the consumer or the previous producer. The consumer reads the results from the buffers in producer order.
    Type: Grant
    Filed: May 28, 1996
    Date of Patent: April 25, 2000
    Assignee: International Business Machines Corporation
    Inventors: Fen-Ling Lin, Bryan F. Smith, Yun Wang
  • Patent number: 6055533
    Abstract: A software system (2) utilizing a filtered priority queue (10) is provided. A filtering module (4) is operable to access a plurality of data records of entities (16, 18, 20, 22, 24, 26 and 28) of a-priority queue and to filter and arrange the data records in a memory storage device (8) to form the filtered priority queue (10). The filtered priority queue (10) comprises a remaining set (12) and a filtered set (14). The filtered set (14) contains a first subset of data records (20, 22, 24, 26, and 28). The first subset of data records (20, 22, 24, 26, and 28) form sublevels of a lattice. The remaining set (12) contains a second subset of data records (16 and 18). The second subset of data records (16 and 18) comprise lattice heads of the lattice. A sorting module (6) is coupled to the filtering module (4). The sorting module (6) is operable to access the remaining set (12) and to order the data records (16 and 18) in the second subset of data records to identify a data record (16) of a most critical entity.
    Type: Grant
    Filed: February 25, 1997
    Date of Patent: April 25, 2000
    Assignee: i2 Technologies, Inc.
    Inventor: John C. Hogge
  • Patent number: 6055559
    Abstract: A status management unit manages a free status capable of invoking a process switch and a critical status. When a process currently being executed is in an input/output process or in a critical status during a message communication, a switch control means controls a control signal for a process switch, such that a process switch does not take place.
    Type: Grant
    Filed: September 19, 1996
    Date of Patent: April 25, 2000
    Assignee: Fujitsu Limited
    Inventors: Toshiyuki Shimizu, Hiroaki Ishihata
  • Patent number: 6052528
    Abstract: A process for the management of multiple inheritance for application in a system or language employing persistent and shared objects. According to this process, the format of an object is maintained unchanged when it is being loaded from persistent space into virtual space. Moreover, each class producing an object is associated with an identifier of the class constant in all those applications utilizing the class as well as through all the recompilations. The structure of the object is thus independent of the address of storage in memory and of the code of the class producing this object. Finally, according to the present process, an addressing path permitting the management of inheritance is imposed via different tables.
    Type: Grant
    Filed: May 14, 1997
    Date of Patent: April 18, 2000
    Assignee: Bull S.A.
    Inventor: Pascal Dechamboux
  • Patent number: 6041363
    Abstract: An interface in a dynamic link library is created which communicates with and provides data translation functions from an application program, such as a test tool, to a device driver. A virtual device driver in an operating system of a computing system is accessed by a calling program to perform and verify the operation of the virtual device driver. A request from the calling program to perform an operation supported by the virtual device driver is decoded in the interface of the dynamic link library. An address of the virtual device driver corresponding to the requested operation is acquired in the dynamic link library.A processing module maintained in the dynamic link library for processing the requested operation is invoked, and data from this module is passed to the virtual device driver in response to the requested operation.
    Type: Grant
    Filed: March 29, 1996
    Date of Patent: March 21, 2000
    Assignee: Sun Microsystems, Inc,
    Inventor: Daniel H. Schaffer
  • Patent number: 6038584
    Abstract: There is disclosed a multi-processor system arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories. The individual processors can, on a cycle by cycle basis, be grouped in any configuration to run in synchronism (but from different instruction streams) with the other processors in that group. More than one such synchronized group can be formed concurrently. A crossbar switch serves to establish the processor memory links and the entire image processor, including the individual processors, the crossbar switch and the memories are contained on a single silicon chip.
    Type: Grant
    Filed: March 15, 1993
    Date of Patent: March 14, 2000
    Assignee: Texas Instruments Incorporated
    Inventor: Keith Balmer
  • Patent number: 6035321
    Abstract: A kernel for enforcing a hierarchical invocation structure prevents upcalls by executing kernel operations during each invocation of code unit of application by another code unit. Kernel operations determine the priority of the invoking unit of code based on the hierarchy of the invocation structure. Only invocations by either lower priority units, or the unit itself are allowed. Once invoked, the kernel operates to establish a priority for the invoked task. The kernel provides various event mechanisms to provide for priority based preemption concurrently with the enforced invocation structure, thus allowing the handling of asynchronous events in a multitasking environment. The event mechanisms allow a unit of code to signal the occurrence of a condition, which may be captured by other code units. The kernel determines the proper code unit for responding to the condition, and employs scope rules to further define the handling operation.
    Type: Grant
    Filed: June 29, 1994
    Date of Patent: March 7, 2000
    Assignee: ACIS, Inc.
    Inventor: Richard Chapman Mays
  • Patent number: 6035124
    Abstract: A fast and efficient way of performing extended global value numbering beyond basic blocks and extended basic blocks on a complete topological ordering of basic blocks in a program. Global value numbering is further extended with a Value Number List, an ordered list of value numbers of an expression, and iterative processing of a worklist containing expressions which are recursively defined. A hash table is used to reduce storage and processing time.
    Type: Grant
    Filed: December 6, 1995
    Date of Patent: March 7, 2000
    Assignee: International Business Machines Corporation
    Inventor: John Shek-Luen Ng
  • Patent number: 6029207
    Abstract: An apparatus and method for the dynamic (execution time) linking of object oriented software components is disclosed. The present invention comprises a computer system including a set of at least two software components. This invention provides a method and means for dynamically linking object oriented software components during run time execution of the program. The present invention includes two main features. First, a query function is provided to allow an application component to determine, during program execution time, the name and location of library classes available for use. Second, the application component can create (instantiate) instances of derived classes of an abstract base class. The application component can manipulate the instantiated object using the abstract interface provided by the base class definition. The implementation of the present invention involves processing at two steps in the software generation cycle.
    Type: Grant
    Filed: August 19, 1997
    Date of Patent: February 22, 2000
    Assignee: Apple Computer, Inc.
    Inventor: Andrew G. Heninger
  • Patent number: 6029188
    Abstract: In an information processing system for architecture model, which comprises a plurality of software modules divided into independent element functions and a work memory area for reading and writing various information as a shared medium, there are provided a work memory area management module 106 for managing history of task phase descriptions delivered to the work memory area as context information, a bid arbiter module 107 for evaluating bids in contract net protocol using the accumulated context information, and a dialog manager module 105 for explaining course of context dependent processing to the user and for providing means to customize the context dependent processing to the user, whereby the software module groups give and take task phase descriptions via the work memory area using the work memory area access procedure, and the bid arbiter module 107 evaluates bids based on the context managed by the work memory area management module 106 so that module groups are operated according to mutual context
    Type: Grant
    Filed: July 18, 1995
    Date of Patent: February 22, 2000
    Assignee: Institute For Personalized Information Environment
    Inventor: Masashi Uyama