Abstract: A computer implemented method and computer system for testing a target software product is presented. The method includes constructing a finite state machine in which portions of the target product are ascribed to states of the state machine. The state machine may correspond to a predetermined test case for the target software product. A number of state functions are provided, each of the state functions performing at least one verification on the target software product. The state functions also may include transitioning from one state to the next, for example, by a "next window" a "previous window" action if the target software program is a windows based program. The state functions may also verify that a current state in which the state machine exists is a correct state, may verify information that is supposed to have been written to a memory is written in fact to the memory, and may verify that the path to the information is correct.

Abstract: The present invention defines a a method, an apparatus and a computer program product for establishing a secure connection between a Java Applet and a secure web server for protocols other than Https via the use of a Java Security Service. More specifically, the present invention uses the web browser's installed certificates to setup and establish an encrypted session between the Java Applet and the secure web server. The secure connection is then used to retrieve the certificates required by the Java security service.

Abstract: A watchdog timer circuit includes a cyclic counter having an overflow signal that functions as a reset pulse to a microprocessor. The timer circuit includes a feature for selectively supplanting the overflow signal to enable in situ programming of the microprocessor.

Abstract: A system for automatic fault detection and recovery in a computer system includes: a system fault detector, a halt time duration counter, and program and hardware recovery signal generators. The system fault detector is connected to a plurality of bus signal lines of a computer system to produce an output signal in response to an existence of an operating signal in the system bus. The halt time counter is operated in response to the output signal of the fault detector and clock signals to produce a set of count values each representing the passage of a predetermined time duration after a vanishing of the output signal of the fault detector. The program recovery signal generator produces a system management interrupt (SMI) signal when seven minutes have elapsed from the detection of the system halt. Also, the hardware recovery signal generator produces a reset signal when eight minutes have elapsed from the detection of the system halt.

Abstract: A network system server that provides password synchronization between a main data store and a plurality of secondary data stores is disclosed. The network system server includes a security server, which is coupled to the main data store, a plurality of clients, which is coupled to the security server for accessing the main data store wherein each client maintains a unique, modifiable password, a password synchronization server, which is coupled to security server and the plurality of secondary data stores, and a password repository, which is coupled to the password synchronization server, that stores the passwords. One of the secondary data stores can retrieve the passwords via the password synchronization server so that each client is able to maintain a single, unique password among the plurality of secondary data stores. Password retrieval is instigated by at least one of the plurality of secondary data stores regardless of the current password status of the secondary data stores.

Abstract: A fault handling process in a computer system subject to CPU design errors and functioning under an operating system (OS) having an integral fault handling module includes the steps of: setting an intercept flag when a central processor fault occurs if the fault is to be directed to a preprocessor; establishing a safestore frame which includes information identifying the type of fault and whether the intercept flag is set; and transferring control to the OS fault handling module; then in the OS fault handling module, determining whether the intercept flag is set; if the intercept flag is not set, handling the fault in the OS fault module; if the intercept flag is set, transferring control from the OS fault module to an Intercept Process written in machine language; and handling the fault in the Intercept Process.

Abstract: A system for generating a gapless series of identity values in a history log maintained in a database by a database management system without adversely impacting database performance. The system comprises the steps of determining a last used identity value independent of an intervening disruptive event that is disruptive to the database management system, generating a next identity value based on the last used identity value, and inserting a record of an event into the history log wherein a change record event contains the next identity value. Determining the last used identity value in the history log depending on whether or not a disruptive event has occurred during normal transaction processing. Absent a disruptive event, the last used identity value is the identity value used in the most recent change record insertion.

Abstract: The present invention utilize the systems described blow to carry out the real time broadcasting on an Internet. Data-collection processing system for collecting and processing the original packages sent by all data-sources connected to the data-collection processor system. Receiving system is used for sending out user's information utilized in the authentication about a user. In addition, the receiving system receives packages of selected kinds of data-source and examines which packages are missing. Also, the receiving system sends out the number representing data-sources of a missing package. Besides, the authentication system is included for examining whether the user is registered, and transmitting the number representing data-source requested by the receiving system to the multi transmitting system. Another function is to assign a source of the most light loading to provide data for the user and sending address of the source to the receiving system.

Abstract: A method of configuring and reconfiguring a computer system based on user authorization is presented wherein at least some users perceive themselves and available system resources as the entirety of the computer system. The resources are configured through use of virtual resources providing predetermined access privileges and configurations for some users. In another aspect, a method is provided of configuring and reconfiguring a computer system based on biometric user input wherein at least some user biometric input is necessary in order to gain authorized access to a system and to configure the system based on the authorized user. The configuration is, preferably, transparent to the user.

Abstract: A method consists in assigning an authorization level (AUTH) to a client object and a "dynamic" sensitivity level (DSL) to a method (or data processing procedure) of a server object (ProcObjSv). The dynamic sensitivity level is computed based on static sensitivity levels (SSLs) at the moment when the server object is instantiated. The authorization level of the client object is passed to the method of the server object when the method of the server object is invoked by the client object, and this authorization level (AUTH) is compared with the dynamic sensitivity level (DSL) of the method in order to control access. The method makes it possible to implement a multi-level security model.

Abstract: An information processing system has a plurality of processor circuits, each of the processor circuits including internal circuits and an internal processing result outputting circuit, the system having an internal data selection circuit connected to each of the processor circuits and at least one fault detection circuit. The internal processing result outputting circuit of each of the processor circuits outputs respective result data processed by respective ones of the internal circuits in the processor circuit. Each of the internal data selection circuit selects and outputs one selected result data output from the internal processing result outputting circuit of each of the processor circuits, at a predetermined timing. The fault detection circuit outputs a result of a comparison among the data selected by the respective internal data selection circuits of the processor circuits or among the data output at each predetermined timing by the processor circuits.

Abstract: A distributed control system wherein status is propagated through the system along with the signal with which the status is associated. The function blocks of the system include rules for propagation of the status through the system. The system may also include function blocks for testing the propagated status to determine if the same is bad and function blocks to force the propagated status to have a certain status. The rules may be customized by the user, for example, to block status propagation through a function block.

Abstract: The content of a document is stored in a file system, while the profile of the document is stored in a messaging system. The profile of the document is accessed upon request, and the document content is accessed based upon the content of the profile.

Abstract: A data allocator which allocates data and redundant data for recovering the data. The data allocator has k storage groups, each of which includes m array files. Each array file includes multiple memory areas for storing the data and the redundant data on a block basis. A redundant group is formed which consists of k memory areas, each of which is selected from the same row of each one of k storage groups, and one of the k memory areas stores the redundant data and the remaining (k-1) memory areas store the data. The redundant data are uniformly allocated to m.sup.k sets of memory areas (D.sub.ij1, D.sub.2j2, . . . , D.sub.kjk) of the same rows of the storage groups, where j.sub.i (j.sub.i =1-m) is the number of the array file in each of the storage groups, and D.sub.kjk is the memory area belonging to k-th storage group and j.sub.k -th array file of the k-th storage group.

Abstract: The present invention relates to a fault detection and automatic recovery apparatus of write-read pointers in FIFO. While storing effective data in a register in writing performance, the apparatus does not unconditionally enable a FULL.sub.-- FLAG signal allotted to the register but confirms the relation of write-read pointers at that time and the EMPTY.sub.-- FLAG signal of a register at which the read pointer is situated and detects the error of FIFO. By selectively enabling the FULL.sub.-- FLAG signal of the register according to the result of detection, it automatically restores the FIFO functions without unnecessary re-initialization or the discontinuation of data transmission attributable thereto.

Abstract: A method and system for remapping physical memory that is malfunctioning. The physical memory has memory locations with addresses. The addresses are ordered from a lowest to a highest address, and each address has bits ordered from a highest-order bit to a lowest-order bit. The system scans physical memory to determine which memory locations are malfunctioning. The system identifies a lowest address and a highest address of the memory locations that are malfunctioning. The system then identifies the highest-order, contiguous bits of the lowest address that are the same as the highest-order, contiguous bits of the highest address. The system generates a remapping value whose highest-order bits are equal to the inverse of the identified highest-order, contiguous bits of the address and whose lowest-order bits are all zeroes. When the system receives an address to access physical memory, the system generates a remapped address by performing a bitwise exclusive-OR of the received address with the remapping value.

Abstract: A method and system for performing performance monitoring within a data processing system whereby a counting function to be performed by a particular counter within the performance monitor is dependent upon a particular event programmed within another counter within the performance monitor so that reprogramming of all code points for each performance counter is not required.

Abstract: A personal computer system capable of preventing unauthorized user's access by way of a chip-in card including a card read and write unit for detecting the insertion or ejection of the chip-in card; a card read and write controller for generating an interrupt in response to the insertion or ejection of the chip-in card; at least one input means for allowing the user to input commands and information to gain access to the computer; and a host controller responsive to the interrupt from the card read and write controller, for preventing the input of commands and/or information from the input means, when the chip-in card is ejected, but allowing input of commands and information from the input means, when the chip-in card is inserted in position of the card read and write unit.

Abstract: A method of testing at least a selected portion of system memory for a microprocessor system is disclosed, the microprocessor system having burst mode capability to transfer data values between the microprocessor and the system memory via a system bus. The method includes the steps of: writing at least a selected portion of system memory with a predetermined test pattern using the burst mode capability of the microprocessor system; reading back values from the at least a selected portion of system memory using the burst mode capability of the microprocessor system; and comparing the values read from the at least a selected portion of system memory with the predetermined test pattern written.

Abstract: Predictive failure analysis of a storage subsystem is efficiently conducted and data quickly recovered from a failed Read operation. This may be implemented in a storage system including a host coupled to a supervising processor that couples to a parity-equipped RAID storage subsystem having multiple HDAs each including an HDA controller and at least one storage medium. In one embodiment, when an HDA experiences an error during a Read attempt, the HDA transmits a recovery alert signal to the supervising processor; then, the processor and HDA begin remote and local recovery processes in parallel. The first process to complete provides the data to the host, and the second process is aborted. In another embodiment, an HDA's PFA operations are restricted to idle times of the HDA. A different embodiment limits HDA performance of PFA to times when the processor is conducting data reconstruction.