Abstract: A plurality of disk drive memories are operatively coupled to a plurality of disk drive controllers. The disk drives are operatively grouped and coupled to a plurality of communication busses, each bus being coupled to a respective disk drive controller. A plurality of segment buffers are coupled to the disk drive controllers and a parity error correction system is coupled to the segment buffers. The error correction system is coupled to an input/output circuit through a plurality of buffers and an interface circuit. A processor communicates with the output buffers, the error correction system, and the segment buffers to control the storage and retrieval of data to and from the array of disk drives. The error correction system establishes a plurality of relatively small parity groups among the disk drives, each parity group having a designated parity drive.

Abstract: A software agent for detecting and removing computer viruses located in attachments to e-mail messages. A client-server computer network includes a server computer and a plurality of client computers. A message system, located at the server computer, controls the distribution of e-mail messages. An anti-virus module, located at the server computer, scans files for viruses. The agent is located at the server computer and provides an interface between the anti-virus module and the message system. The agent can operate both on a real-time basis and at preset period intervals. E-mail messages that are sent internally within the network can be scanned, e.g., Intranet e-mail messages. In addition, e-mail messages received over the Internet can be scanned.

Abstract: Predictive failure analysis of a storage subsystem is efficiently conducted and data quickly recovered from a failed Read operation. This may be implemented in a storage system including a host coupled to a supervising processor that couples to a parity-equipped RAID storage subsystem having multiple HDAs each including an HDA controller and at least one storage medium. In one embodiment, when an HDA experiences an error during a Read attempt, the HDA transmits a recovery alert signal to the supervising processor; then, the processor and HDA begin remote and local recovery processes in parallel. The first process to complete provides the data to the host, and the second process is aborted. In another embodiment, an HDA's PFA operations are restricted to idle times of the HDA. A different embodiment limits HDA performance of PFA to times when the processor is conducting data reconstruction.

Abstract: A semiconductor device testing fixture is provided in which the performance tests of a semiconductor device can be executed without increasing the time for testing and the equipment investment for a semiconductor tester with an increase in the practical operating frequency of a tested semiconductor device. A semiconductor device testing fixture (1A) has input terminals (2, 3, 4) and an output terminal (15) for receiving and sending a signal together with a semiconductor tester (18). These terminals are connected to the predetermined terminals of the semiconductor tester (8). A memory (7) which can perform first in first out operation is mounted as signal holding means on the semiconductor device testing fixture (1A).

Abstract: The invention is a generalized process for dynamically restoring traffic in the event of an outage in a telecommunications network. A Centralized Processing System (CPS) receives alarms from communications ports of diverse network equipment (DNE) elements. The CPS then proceeds to analyze and correlate the alarms in an effort to isolate the location of the outage. In doing so, the CPS utilizes a Network Topology database that is preferrably updated in real-time with topology data obtained directly from the DNE network. The CPS will then identify and prioritize all traffic-bearing trunks impacted by the outage. The CPS then generates and implements a restoral route for each impacted trunk by issuing appropriate reroute command to the DNEs. If a DNE responds with an indication that a command failed and that its particular restoral segment is not possible, the CPS updates Network Topology database to indicate this segment as unavailable and proceeds to generate another restoral route.

Abstract: Traps from network devices are filtered and prioritized. Filtering and prioritization can be performed on specific types of traps, traps from specific devices and traps from specific enterprises. Filtering is performed to reduce the number of traps that are processed, and prioritization is performed to indicate the relative importance of the traps. The filtering and prioritization can be performed by a trap daemon, which is executed by a network manager. Priorities and filters can be assigned to the traps, devices and enterprises by a network administrator. This provides the network administrator with great flexibility in managing the traps according to the situation at hand.

Abstract: An information accessing method permits the user data belonging to a client-server system to be accessed by a user belonging to another client-server system under proper security and controls the permission for accessing the user data according to the security ranks of the user whose data is to be accessed and the user who wants to access the data. When a client unit issues a request for accessing the user data of the user belonging to the other client-server system, the request for access is sent to an ID conversion unit through a user ID management unit. The ID conversion unit operates to convert a user ID into a guest ID by referring to an ID conversion table, and then sends the request for access to a user ID management unit. The user ID management unit makes sure that the guest ID is registered by referring to the user ID table.

Abstract: An electronic monetary system provides for transactions utilizing an electronic-monetary system that emulates a wallet or a purse that is customarily used for keeping money, credit cards and other forms of payment organized. Access to the instruments in the wallet or purse is restricted by a password to avoid unauthorized payments. When access is authorized, a graphical representation of the payment instruments is presented on the display to enable a user to select a payment method of their choice. Once a payment instrument is selected, a summary of the goods for purchase are presented to the user and the user enters an electronic approval for the transaction or cancels the transaction. Electronic approval results in the generation of an electronic transaction to complete the order.

Abstract: Predictive failure analysis of a storage subsystem is efficiently conducted and data quickly recovered from a failed Read operation. This may be implemented in a storage system including a host coupled to a supervising processor that couples to a parity-equipped RAID storage subsystem having multiple HDAs each including an HDA controller and at least one storage medium. In one embodiment, when an HDA experiences an error during a Read attempt, the HDA transmits a recovery alert signal to the supervising processor; then, the processor and HDA begin remote and local recovery processes in parallel. The first process to complete provides the data to the host, and the second process is aborted. In another embodiment, an HDA's PFA operations are restricted to idle times of the HDA. A different embodiment limits HDA performance of PFA to times when the processor is conducting data reconstruction.

Abstract: A disk array system includes a disk array, an array controller, an offtrack detecting unit, an error processing unit, an offtrack measuring unit, a reformat control unit, and a reformat processing unit. The disk array includes a plurality of disk devices storing a plurality of data in parallel and storing redundant data used for restoring data lost if one of the plurality of data is lost. The array controller controls input from or output to the disk array based on a request from an upper system, such as a host computer. The offtrack detecting unit is provided in each of the disk devices for detecting offtrack and informing the array controller of the offtrack. Further, an error processing unit is provided in the array controller for logically disconnecting a disk device having communicated information if offtrack detection information is received from the offtrack detecting unit, and for issuing a diagnostic I/O command.

Abstract: An electronic device having addressable storage elements and a bus so that the storage elements are accessible via the bus, an address register connected to the bus, a data register connected to the bus, terminals for serial scan-in and scan-out, a scanable emulation control register coupled to the terminals, and a selecting circuit responsive to bits in the emulation control register for coupling the address register and the data register to the terminals to enable scanning of the address and data registers.

Abstract: In a computer implemented method, a client computer connected to a public network such as the Internet makes a request for an intranet resource to a tunnel of a firewall isolating the intranet from the Internet. The request is made in a public message. The tunnel sends a message to the client computer to redirect to a proxy server of the tunnel. The client computer send a token and the request for the resource the proxy server. If the token is valid, the request is forwarded to the intranet, otherwise, the user of the client computer must first be authenticated.

Abstract: A method for executing software which is stored in an external memory attached to console equipment having a CPU uses software assets advantageously. The console equipment is designed to bank switch from a BIOS ROM included in the console equipment to the software stored in the external memory during an initialization routine, to check the genuineness of the software during a security check routine, and to execute the software by the CPU of the console equipment during a program executing routine if the software is judged to be genuine during the security check routine. In some embodiments of the method, the program is executed by the CPU during the program executing routine after the security check routine, at least, has been skipped. In other embodiments, the security check is always forced to be successful. Circuitry for performing the method is also disclosed.

Abstract: A method for frame synchronization including the detection of an n-bit pattern with predetermined characteristics in a bitstream is described. The subject method includes the steps of extracting a first set of m bits, with m being smaller than or equal to n, from a first position in said bitstream, deriving from said first set an address of a location in a first memory, deriving from the contents of said location in said first memory at least one second position in said bitstream and at least one second set of bits to be extracted therefrom until said n-bit pattern is detected in said bitstream. An apparatus for performing the subject method is additionally described.

Abstract: A circuit for preventing malfunctions in a microprocessor or a central processing unit due to static electricity includes: malfunction detection circuitry for detecting a malfunction of the microprocessor from a predetermined signal generated from the microprocessor; a reset signal generator for generating a reset signal for resetting the microprocessor according to a malfunction detection signal generated from the malfunction detection circuitry; and reset summing circuitry for generating a synthesized reset signal by synthesizing the reset signal with a power reset signal, and resetting the microprocessor by providing the synthesized reset signal to the microprocessor.

Abstract: An address generator provided on an error control chip of an optical disk storage for addressing a plurality of working buffers accessed by a CPU, an optical disk drive (ODD), and encoder/decoder circuitry during error correction operations. The address generator comprises a loading address generator that produces an adop address signal to provide linear buffer access for the CPU and ODD when data are supplied from and to the CPU and ODD for encoding and decoding. A processing address generator produces an adex address signal that provides interleaving and random buffer access for the encoder/decoder circuitry during data encoding and decoding operations. A buffer rotation control circuit produces address and data bus control signals to provide the rotation of the buffers between the CPU, ODD, and encoder/decoder circuitry in various encoding and decoding cycles to support a pipeline error control arrangement.

Abstract: A solid state disc (SSD) Memory comprising the following functional blocks: a memory block (DATA ARRAY) wherein check data bytes are written; a transcoder memory block (SCRAMBLE RAM) which contains the table enabling the reallocation of the data matrix addresses, wherein redundant rows are included; a block (SCRAM DEC) for decoding the addresses of the decoder table; a logic block (FUSE LOGIC) to enable a step to be executed to locate any non-useable row and to substitute said redundant rows therefor; an error correction code (ECC) block for implementing the error correction algorithm; an input buffer block (LOGICAL ROW ADDRESS BUFFER) for storing the row addresses coming from the external bus; a non-volatile memory block, programmed during the test stage and available to a possible processor for handling the contents of the transcoder memory (SCRAMBLE RAM); a word counter block (WORD COUNTER) that is driven from the external clock signal (clock) and counts the number of the addressed words and generates the

Abstract: A serial input/output circuit with an automatic transfer function can easily re-transfer correct data even if a transfer error occurs during automatic transfer. When the transfer of one data has been completed, an automatic transfer data pointer normally automatically updates its contents and indicates an address in an automatic transfer RAM, which corresponds to data to be next transferred. An error generation active circuit makes an error control signal significant when an error detecting circuit detects an error produced in data or the occurrence of the error in the data is notified from a transfer opposite party. When the error control signal is made significant, the automatic transfer data pointer and the transfer counter do not update their values.

Abstract: A method and apparatus are for maintaining a cyclic redundancy check (CRC) byte is described which eliminates additional input/output (I/O) transactions for the case when a write to a partial sector is required while the CRC byte is maintained for an entire sector. The method includes performing an XOR operation between the partial write data and the data it is to displace, and then performing an XOR operation between the old CRC byte associated with the sector and the result of the XOR operation between the partial write data and the data it is to displace.

Abstract: A data communication system includes a host (12) having a memory and a remote (16) that communicate data. A security system (14) is coupled to the remote (16) and the host (12), and spawns an interactive process in response to the remote (16) requesting access to the host (12). The interactive process has selected access to the memory of the host (12), and interacts with the remote (16) to provide the selected access. The security system (14) may include a communications module (50), a control module (60), a mailbox module (62), an auto connect module (64), a log module (66), and an exits module (68).