Abstract: A method, apparatus and program product for performing a disruptive recovery in a data processing system including establishing an upper limit of delay that may be taken before starting a recovery process and establishing a set time for stalling. A first event for which a recovery process is normally started is then received and the start of the recovery process is stalled for the set time for stalling after receipt of the first event. Events subsequent to the first event are received until either the time between the receipt of successive events exceeds the set time for stalling, or until the upper limit of delay between the receipt of the first event and the receipt of the last received event is exceeded. After the time limit is exceeded, the recovery process is performed and the operation is started over with the receipt of a new first event.

Abstract: A fault-tolerant system has a predetermined system function and comprises a plurality of functional blocks. The fault-tolerant system uses selected ones of the functional blocks to construct the predetermined system function and uses a remaining one of the functional blocks to recover the predetermined system function when one of the selected functional blocks becomes a faulty functional block. The fault-tolerant system comprises a memory device for memorizing a plurality of block connection relationships each of which is representative of a functional block connection for providing the predetermined system function. A detecting device detects the faulty functional block to produce a fault signal. An accessing device accesses the memory device in response to the faulty signal to select a selected one of the block connection relationships that does not include the faulty functional block. A recover device recovers the predetermined system function in accordance with the selected block connection relationship.

Abstract: A method for recovering data from a cache memory of a second storage controller by access to a cache memory of a first storage controller is presented. The storage controllers are coupled by a private common data path. The method includes copying metadata corresponding to the data stored in the cache memory of the second storage controller to the cache memory of the first storage controller through the private common data path. The metadata may include pointers to and the size of the data. After copying the metadata pointers, the data in the cache memory of the second storage controller is established in the cache memory of the first storage controller. As a result, the entire set of data does not need to be totally recovered to the hard disk before resuming host communications in a recovery operation, which may take a relatively long time.

Abstract: An external storage system has a storage unit for storing data and a plurality of storage controllers for controlling data transfer between an upper level system and the storage unit. Each storage controller has a data buffer for temporarily storing data and a controller for controlling the operation of the storage controller. The external storage system has a management memory for storing management information of the plurality of storage controllers each of which accesses this memory to monitor the operation states of other storage controllers. The external storage system has a first storage controller for processing an input-output request from the upper level system and a second storage controller for standing by for backup for a failed storage controller.

Abstract: An incremental backup system includes a storage unit, which is accessed in block units of a predetermined size, for storing data to be backed up. Difference map information stored in the storage unit records the latest backup generation number, indicating when data in each block has been updated. A latest update generation management mechanism manages backup generation numbers for each block. A difference management mechanism inputs and stores backup data in a backup unit. The backup data includes data in a block of the storage unit which is updated in a specified backup generation based on the difference map information, a position of the block in the storage unit, and a backup generation in which the block has been updated.

Abstract: Predictive failure analysis of a storage subsystem is efficiently conducted and data quickly recovered from a failed Read operation. This may be implemented in a storage system including a host coupled to a supervising processor that couples to a parity-equipped RAID storage subsystem having multiple HDAs each including an HDA controller and at least one storage medium. In one embodiment, when an HDA experiences an error during a Read attempt, the HDA transmits a recovery alert signal to the supervising processor; then, the processor and HDA begin remote and local recovery processes in parallel. The first process to complete provides the data to the host, and the second process is aborted. In another embodiment, an HDA's PFA operations are restricted to idle times of the HDA. A different embodiment limits HDA performance of PFA to times when the processor is conducting data reconstruction.

Abstract: An error detection code decoding device in which information codes obtained through a transmission path and original check codes which correspond to the information codes and which are obtained through the transmission path are input. A processor receives the input information codes and forms restored check codes by using the information codes, the processor including lookup tables for inputting the information codes as addresses and reading out data regarding the restored check codes. A detector detects whether or not the restored check codes and the original check codes coincide and outputs an error detection signal indicative of the presence or absence of an error.

Abstract: A method and system provides a special purpose or embedded system developer with the ability to confirm the correct operation of a computer program designed to operate on a target system whose processing and storage capabilities may be more austere than the host system upon which the computer program is designed and tested. A key feature of the method and the system enables a developer to execute and debug an application program on a host system while observing and testing the operation of the program through the input/output of the target system. Another feature of the method and system is an application loader that dynamically sizes and, as necessary, reconfigures the available memory to permit multiple applications to reside simultaneously on the target system by resolving addresses in the target system at the time an application of interest is downloaded to the target system.

Abstract: Data is recovered despite a single point of failure in a data exchanging system while accommodating scaleable data transfer rate performance. In the environment of at least two disk array controllers, a serial dumping scheme assists in recovery of data from a fast memory. It is imperative to avoid loss of write data from a host computer which is received and acknowledged but not yet stored in a disk medium. The configuration ensures that at least one of the controllers will handle the data so as to correct single failure point errors and properly store that data on one of the disks of an array. A fast memory providing a buffer between a remote host computer and arrays of data storage media is managed so that data received for writing is duplicated for reliability of storage while data for reading to the host computer is manipulated with an enhanced bandwidth of fast memory operation.

Abstract: An automatic recovery system for a network appliance features a watchdog processor that monitors operation of the appliance and initiates reboot as necessary. A primary and a secondary boot partition are provided in the system, in some embodiments on the same mass storage device, and in other embodiments on a different mass storage device. In the event reboot is unsuccessful from the primary boot partition, reboot is initiated from the secondary boot partition. The watchdog processor executes automatic recovery software stored in a non-volatile storage device, which may be a part of the same IC as the watchdog processor.

Abstract: Read and write addresses on the local and line sides of a SONET elastic store are compared at least twice in order to determine any ambiguity in the comparison and, if so determined, foregoing any pointer adjustments that would otherwise have been made.

Abstract: In a memory system comprising a plurality of memory units each of which possesses unit-level error correction capabilities and each of which is tied to a system level error correction function, memory reliability is enhanced by providing a mechanism for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.