Abstract: Washing a microelectronic substrate with an ozonated solution following planarization and proceeding removal of a native oxide layer through acid etching.

Abstract: There is provided a metal etching mask fabrication method. Chrome is first sputtered on a silica layer and a photoresist, which is thicker than the chrome layer, is deposited on the chrome layer. The photoresist layer is patterned, a first nickel is sputtered on the photoresist pattern layer and onto a first portion of the chrome layer exposed by the patterning. A second nickel layer is formed on the portions of the first nickel layer in contact with the first portion of the chrome layer by electroplating. The photoresist pattern has side walls having acute angles to prevent contact between the first nickel layer on the photoresist and the second nickel layer on the first portion of the chrome layer. The photoresist pattern layer and the first nickel layer formed on the photoresist pattern layer are removed using a solvent, and the chrome layer is removed by dry etching in plasma using a gas.

Abstract: A plasma etching method using selective polymer deposition, and a method of forming a contact hole using the plasma etching method are provided. The plasma etching method uses a method of reinforcing an etch mask by selectively depositing polymer on only a photoresist pattern, which is an etch mask. That is, a dielectric film is plasma etched for a predetermined period of time using the photoresist pattern as an etch mask, and polymer is selectively deposited on only the photoresist pattern which is thinned by plasma etching, thereby forming a polymer layer. Following this, the dielectric film is plasma etched using the photoresist pattern and the polymer layer as a mask. Thus, dielectric film etching providing high resolution and an excellent profile can be performed using the thinned photoresist pattern as a mask, and a contact hole and a self-aligned contact hole each having a very high aspect ratio, and a self-aligned contact hole having an excellent profile, can be formed.

Abstract: The present invention provides a method for the simultaneous removal of an oxygen and/or nitrogen-containing dielectric antireflective coating (“DARC”) during plasma etching of an underlying layer in a film stack. According to the method of the invention, the film stack is etched using a plasma containing reactive fluorine species. The concentration of reactive fluorine species within the plasma is controlled based on one or more of the following factors: the oxygen content of the antireflective coating, the nitrogen content of the antireflective coating, the thickness of the antireflection coating layer, and the thickness of the underlying film stack layer. The disclosure of the invention provides preferred combinations of plasma source gases which provide for the simultaneous removal of an oxygen and/or nitrogen-containing DARC layer during etching of an underlying etch stack layer, where the underlying stack layer comprises a metal silicide, polysilicon, or a metal.

Abstract: A method of manufacturing a semiconductor device provided with a first insulating film and a barrier film on a conductive region and an opening portion in the first insulating film and the barrier film, the method comprising the steps of: forming a first opening portion in the barrier film reaching the first insulating film; forming a second insulating film at least on the first insulating film in the first opening portion; and forming a second opening portion smaller than the first opening portion and reaching the conductive region by simultaneously boring a hole into the first insulating film and the second insulating film in the first opening portion.

Abstract: A giant magnetoresistance (GMR) sensor is formed using a self organizing diblock copolymer as an etching mask. The diblock copolymer is deposited over a magnetic layer and is self organized into regions of two discrete thicknesses; higher thickness island regions separated by lower thickness valley regions. After the diblock layer is self organized, an etching of process is performed to remove the polymer material from the valley regions as well as the underlying magnetic material. After etching, a patterned magnetic thin film of submicron islands of magnetic material, preferably having a diameter in the single domain range, remain under the mesa region. The islands are interconnected by a non-magnetic, conductive layer with electrical contacts coupled thereto to complete the GMR sensor. When the sensor is not subjected to a magnetic field, the magnetic alignment of the islands is random, and electron scattering results in a high resistance state.

Abstract: In accordance with the present invention, a method for employing and removing inorganic anti-reflection coatings, includes the steps of providing a first dielectric layer on a semiconductor device structure to be processed, the first dielectric layer being selectively removable relative to the semiconductor device structure, and forming an inorganic dielectric anti-reflection coating (DARC) on the first dielectric layer, the DARC being selectively removable relative to the first dielectric layer. A resist layer is patterned on the DARC. The resist is selectively removable relative to the DARC. The semiconductor device structure is etched, and the resist layer, the DARC and the first dielectric layer are selectively removed.

Abstract: A method of manufacturing a ridge-shaped 3-dimensional waveguide, has the steps of: forming a crystal film made of a second ferroelectric oxide non-linear crystal having a refractive index higher than that of a substrate made of a first ferroelectric oxide non-linear crystal on the substrate; forming a metal film on the crystal film; forming a mask by etching the metal film; and forming a ridge portion by selectively removing the crystal film through the mask by a dry etching method.

Abstract: A method for fabricating a semiconductor device including a conductive pattern having a first layer including Ti and a second layer including W is presented. The method includes the steps of patterning the conductive pattern by a dry etching and exposing the conductive pattern after the step of the patterning to a plasma containing O, thereby removing the remaining Cl which induces an aftercorrosion problem of the conductive pattern containing the Ti.

Abstract: Etching end point judging method that includes the following steps in a dry etching end point judging method having a step of reducing noise of input signal waveforms using first digital filter, a step of obtaining a differential coefficient (primary or secondary) of a signal waveform from differential processing by operation circuit, a step of obtaining a smoothed differential coefficient value by reducing the noise components of the time series differential coefficient waveform that was obtained in the previous step, using the second digital filter, and a step of judging an etching end point by comparing the smoothed differential coefficient value and a preset value using discrimination method.

Abstract: Metal nitride and metal oxynitride extrusions often form on metal silicides. These extrusions can cause short circuits and degrade processing yields. The present invention discloses a method of selectively removing such extrusions. In one embodiment, a novel wet etch comprising an oxidizing agent and a chelating agent selectively removes the extrusions from a wordline in a memory array. In another embodiment, the wet etch includes a base that adjusts the pH of the etch to selectively remove certain extrusions relative to other substances in the wordline. Accordingly new metal silicide structures can be used to form novel wordlines and other types of integrated circuits.

Abstract: Methods of forming conductive capacitor plugs, methods of forming capacitor contact openings, and methods of forming memory arrays are described. In one embodiment, a conductive capacitor plug is formed to extend from proximate a substrate node location to a location elevationally above all conductive material of an adjacent bit line. In another embodiment, a capacitor contact opening is etched through a first insulative material received over a bit line and a word line substantially selective relative to a second insulative material covering portions of the bit line and the word line. The opening is etched to a substrate location proximate the word line in a self-aligning manner relative to both the bit line and the word line. In another embodiment, capacitor contact openings are formed to elevationally below the bit lines after the bit lines are formed. In a preferred embodiment, capacitor-over-bit line memory arrays are formed.

Abstract: A new method is provided for creating a dual damascene structure. Two layers of dielectric are deposited in sequence. The lower layer of dielectric is the via dielectric and is selected such that it has a low etching rate (when compared with the upper layer of dielectric) and results in different volatile gas during the etch of the via. A first photoresist is patterned for the via, the etch for the via etches through both layers of dielectric. A second layer of photoresist is patterned for the trench etch, due to the difference in etch rate between the two layers of dielectric, the trench of the dual damascene structure is etched without further affecting the via etch in the lower layer of dielectric.

Abstract: A method for processing a semiconductor wafer with a plasma using continuous RF power for a first phase of wafer processing and with pulsed RF power for a second phase of wafer processing.

Abstract: Silicon carbide is used for a hardmask for the isolation dielectric etch and also serves as an etch stop for chemical-mechanical polishing. Alternatively, silicon carbonitride or silicon carboxide can be used.

Abstract: A new method of etching metal lines with reduced microloading effect is described. Semiconductor device structures are provided in and on a semiconductor substrate and covered with an insulating layer. A barrier metal layer is deposited overlying the insulating layer and a metal layer is deposited overlying the barrier metal layer. The metal layer is covered with a photoresist mask wherein there are both wide spaces and narrow spaces between portions of the photoresist mask. The metal layer is etched away where it is not covered by the photoresist mask wherein the barrier metal layer is reached within the wide spaces while some of the metal layer remains within the narrow spaces. The metal layer remaining within the narrow spaces is selectively etched away. Thereafter, the barrier metal layer not covered by the photoresist mask is etched away wherein the insulating layer is reached within the wide spaces while some of the barrier metal layer remains within the narrow spaces.

Abstract: A method of forming wires for semiconductor devices can restrict increase of a wires resistance and a contact resistance of the semiconductor device by forming a plug without generating a void or keyhole, and includes a step of forming an insulation film on lower wires, a step of forming a contact hole on the lower wires by selectively etching the insulation film, a step of performing a precleaning process by using an argon sputtering method until the lower wires at the lower portion of the contact hole are etched at a predetermined depth, a step of forming a plug by depositing a tungsten in the contact hole, and a step of forming upper wires on the plug and the second insulation film. A re-deposition layer consisting of a material of the lower wires is formed at the inner walls of the contact hole in the precleaning process, and thus a whole process is simplified by omitting a step of forming a glue layer or adhesion layer.

Abstract: A method of producing a chromium mask, said method comprising forming a chromium film on a mask substrate, forming a resist layer on the chromium film, patterning the resist layer in desired shape, performing plasma treatment with a fluorine-containing gas on the resist pattern, and finally performing dry etching on the chromium film by using the resist pattern as a mask.

Abstract: An inlaid interconnect fabrication method using a silicon carbide polish stop layer for protection of mechanically weak dielectric such as porous silicon dioxide (xerogel) during chemical mechanical polishing.

Abstract: An improved method for producing optically smooth surfaces in silicon wafers during wet chemical etching involves a pre-treatment rinse of the wafers before etching and a post-etching rinse. The pre-treatment with an organic solvent provides a well-wetted surface that ensures uniform mass transfer during etching, which results in optically smooth surfaces. The post-etching treatment with an acetic acid solution stops the etching instantly, preventing any uneven etching that leads to surface roughness. This method can be used to etch silicon surfaces to a depth of 200 &mgr;m or more, while the finished surfaces have a surface roughness of only 15-50 Å (RMS).