Abstract: An extrusion-free wet cleaning process for post-etch Cu-dual damascene structures is developed. The process includes the following steps: (1). providing a wafer having a silicon substrate and at least one post-etch Cu-dual damascene structure, the post-etch Cu-dual damascene structure having a via structure exposing a portion of a Cu wiring line electrically connected with an N+ diffusion region of the silicon substrate, and a trench structure formed on the via structure; (2). applying a diluted H2O2 solution on the wafer to slightly oxidize the surface of the exposed Cu wiring line; (3). washing away cupric oxide generated in the oxidation step by means of an acidic cupric oxide cleaning solution containing diluted HF, NH4F or NH2OH; and (4). providing means for preventing Cu reduction reactions on the Cu wiring line.

Abstract: A method of polishing a film formed on a wafer includes steps of polishing a film formed on a surface of a wafer which is chucked by a wafer chuck and set on a polishing disk so that the film faces the polishing disk, irradiating a plurality of portions of the film under polishing process with lights having different wavelengths from one another through a plurality of holes formed in the polishing disk, detecting lights reflected from the plurality of portions of the film caused by the irradiation, evaluating a thickness distribution of the film from information of an intensity ratio of the detected reflected lights, and controlling a pushing pressure of the wafer chuck according to the evaluated thickness distribution under polishing process.

Abstract: Slurries for use in the chemical mechanical polishing (CMP) of copper and copper diffusion barriers that reduce pattern sensitive erosion of an underlying dielectric layer include at least one surfactant. Inclusion of surfactants, such as cetyltrimethylammonium bromide in a slurry mixture can reduce pattern sensitive erosion of dielectric materials such as silicon oxide, and fluorinated oxides of silicon that would otherwise occur during CMP of copper and copper diffusion barriers as is typical in the formation of copper interconnect lines in integrated circuits.

Abstract: A method of etching a low dielectric constant material with an aqueous solution of hydrofluoric acid and hydrochloric acid. The etching solution is particularly useful on low dielectric constant materials that are water repulsive or hydrophobic. The weight ratio of hydrofluoric acid to hydrochloric acid in the aqueous solution ranges from 1:3 to 4:1.

Abstract: A method for forming a stackable wafer for use in an implantable device is provided. The method comprises forming an opening extending substantially through the wafer. Thereafter, conductive material is deposited within the opening to substantially fill the opening. A bump is then formed on an upper surface of the wafer adjacent the conductive material, and a contact pad is formed on a lower surface of the wafer adjacent the conductive material. A second wafer formed using substantially the same process may then be stacked on top of the first wafer with the bump of the first wafer being in contact with the contact pad of the second wafer. A soldering process may then be used to couple the adjacent pad and wafer for physically mounting the wafers and providing electrical connectivity therebetween.

Abstract: In a production process of a semiconductor device, planarizing of a wafer surface pattern can be performed to attain high planarity, good uniformity in the removal amount and improved controllability. This process include a step of planarizing a semiconductor wafer, from which at least two different films have been exposed, by polishing with a grindstone and a dispersant-containing processing liquid.

Abstract: An Al film is formed on a barrier metal covering a thin film resistor to have a first opening. A photo-resist is formed on the Al film and in the opening, and is patterned to have a second opening having an opening area smaller than that of the first opening and open in the first opening to expose the barrier metal therefrom. Then, the barrier metal is etched through the second opening. Because the barrier metal is etched from an inner portion more than the opening end of the first opening, under-cut of the barrier metal is prevented.

Abstract: A method of processing a substrate, where the substrate is transferred from an ambient environment into a clean environment. The substrate is heated to at least a first temperature within the clean environment, and then maintained at no less than the first temperature within the clean environment. The substrate is selectively transferred within the clean environment to more than one processing chambers, and processed in the more than one processing chambers. The substrate is transferred from the clean environment into the ambient environment.

Abstract: In general, the present invention is directed to a method of using slurry waste composition to determine the amount of metal removed during chemical mechanical polishing processes, and a system for accomplishing same. In one embodiment, the method comprises providing a substrate having a metal layer formed thereabove, performing a chemical mechanical polishing process on the layer of metal in the presence of a polishing slurry, measuring at least a concentration of a material comprising the metal layer in the polishing slurry used during said polishing process after at least some of said polishing process has been performed, and determining a thickness of the layer of metal removed during the polishing process based upon at least the measured concentration of the material comprising the metal layer.

Abstract: A modified facet is disclosed to prevent blown gate oxide and increase etch chamber life. The modified facet etch is a two-stage process. The first stage is a plasma sputter etch to form a facet profile. The first stage etch is terminated prior to reaching the target depth for the etching process. The second stage etch is a reactive ion etch which directionally follows the facet profile to reach the target depth.

Abstract: A semiconductor wafer cleaning formulation, including 1-21% wt. fluoride source, 20-55% wt. organic amine(s), 0.5-40% wt. nitrogenous component, e.g., a nitrogen-containing carboxylic acid or an imine, 23-50% wt. water, and 0-21% wt. metal chelating agent(s). The formulations are useful to remove residue from wafers following a resist plasma ashing step, such as inorganic residue from semiconductor wafers containing delicate copper interconnecting structures.

Abstract: A method of manufacturing a wireless suspension blank wherein three-layered laminate formed of a metallic layer having a spring property and a conductive layer laminated on the metallic layer through an electrically insulating layer are used. The laminate used is a laminate in which an insulating layer is formed of a core-insulating layer and adhesive layers laminated on both sides of the core-insulating layer, and the ratio of higher etching rate to lower etching rate of the respective layers of the insulating layer is between 6:1 and 1:1. The metallic layer and the conductive layer are processed by the photo etching method. The insulating layer is processed by the wet etching method.

Abstract: A micro-etching composition and a printed circuit board fabricated by using the micro-etching composition are provided. The micro-etching composition, comprising a main ingredient consisting of sulfuric acid and hydrogen peroxide and an assisting ingredient consisting of phenyltetrazole and a chloride ion source, can continuously treat the surface of copper and copper alloys to produce fine microscopic pits for improved adhesion to resins without producing a brown or black deposit. The printed circuit board exhibits excellent adhesion between inner layer circuit patterns and insulation resin layers, and is free from haloing.

Abstract: The subject matter described herein involves an improved etch process for use in fabricating integrated circuits on semiconductor wafers. The selectivity of the etch process for silicon carbide versus silicon oxide, organo silica-glass or other low dielectric constant type material is enhanced by adding hydrogen (H2) or ammonia (NH3) or other hydrogen-containing gas to the etch chemistry.

Abstract: A method of removing ruthenium silicide from a substrate surface which comprises exposing the ruthenium silicide surface to a solution containing chlorine and fluorine containing chemicals. In particular, said solution is designed to react with said ruthenium silicide film such that water-soluble reaction products are formed.

Abstract: According to one embodiment (300), a method of forming a self-aligned contact can include forming adjacent conducting structures with sidewalls (302). A first insulating layer may then be formed without first forming a liner (304), such as a liner that is conventionally formed to protect underlying conducting structures and/or a substrate. A contact hole may then be etched between adjacent conducting structures (306). Contact structures may then be formed (308).

Abstract: A cleaning agent for a semiconductor device contains a hydroxide, water and a compound expressed in the following general formula (I) and/or the following general formula (II): HO—((EO)x—(PO)y)z—H  (I) R—[(EO)x—(PO)y)z—H]m  (II) Thus provided is a cleaning agent for a semiconductor device, which is so improved as not to disconnect a wire or an embedded conductive layer.

Abstract: A colored, transparent film-forming composition, which is made up of (a) a reaction product of an epoxy group-containing alkoxysilane (a-1) and an amino group-containing alkoxysilane (a-2) having active hydrogen therein, (b) an acid catalyst, (c) an alkali-soluble UV absorber, (d) at least one solvent selected from organic solvents having a boiling point of 100 to 250° C., and (e) a dye and/or a pigment, has a good coating performance and room temperature curing characteristic and can provide a film having good film strength and film removability after use. The coating method of the composition and the removing method of the film obtained from the composition are also described.

Abstract: A method is disclosed for manufacturing a semiconductor device. Initially, a conductive layer is formed over a cell array region, in which high-integrated devices are formed, and over a non-cell region, which functions to assist a proper formation of the cell array region. An etching mask pattern is then formed over the conductive layer to form a conductive pattern over the cell array region and to remove the conductive layer formed on the non-cell region. The conductive pattern is actually formed by etching the conductive layer. An ion-assisted plasma etching is then implemented to form a pattern on the cell array region. This prevents the generation of arcing caused by independent conductive patterns formed on the non-cell region during the ion-assisted plasma etching.

Abstract: A method of forming a metal wiring in a semiconductor device is disclosed. In order to improve a low deposition speed in the process technology by which a damascene pattern of an ultra-fine structure is filled with copper by CVD method, a CECVD method is disclosed by which a chemical enhancer layer for increasing the deposition speed of copper is formed and the damascene pattern is then filled by means of MOCVD method using a copper precursor which forms a copper wiring. A diffusion prevention film is formed on the sidewall of the damascene pattern in the shape of a spacer in order to prevent an increase of the via resistance by the diffusion of copper into the sidewalls of the damascene pattern. A chemical enhancer layer is selectively formed on a lower metal layer that is exposed by the damascene pattern, thus allowing a selective partial filling of the damascene pattern. Therefore, copper filling in an ultra-fine structure is facilitated which also minimizes the electrical resistivity of the copper wiring.