Patents Examined by Lynne A. Gurley
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Patent number: 10043850Abstract: An HV-LED module having 3D light-emitting structure and a method for manufacturing the HV-LED module are disclosed. The HV-LED module has at least two stacked parts of substage LEDs that each have an independent light-emitting structure and are bonded in a staggered pattern, and the substage LEDs are connected in series to form the 3D light-emitting structure, thereby significantly increasing light-emitting power per unit area, downsizing a high-voltage chip module using it by nearly two times, and effectively reducing packaging costs for the HV-LED module.Type: GrantFiled: March 18, 2016Date of Patent: August 7, 2018Assignee: Xiamen Changelight Co., Ltd.Inventors: Zhiwei Lin, Kaixuan Chen, Yong Zhang, Xiangjing Zhuo, Wei Jiang, Tianzu Fang, Yinqiao Zhang, Xiangwu Wang
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Patent number: 10043792Abstract: An apparatus including an electrostatic discharge (ESD) protection device comprising a semiconductor having first, second and third regions arranged to form a transistor, wherein the first region is doped with a first impurity of a first conductivity type and is separated from the second region which is doped with a second impurity of a second conductivity type opposite the first type, and wherein a dimensional constraint of the regions defines an operational threshold of the ESD protection device. In one example, the separation between a collector and an emitter of a bipolar transistor defines a trigger voltage to cause the electrostatic discharge protection device to become conducting. In another example, a width of a bipolar transistor base controls a holding voltage of the electrostatic discharge protection device.Type: GrantFiled: November 8, 2016Date of Patent: August 7, 2018Assignee: Analog Devices, Inc.Inventors: Edward John Coyne, Patrick Martin McGuinness, Paul Malachy Daly, Bernard Patrick Stenson, David J. Clarke, Andrew David Bain, William Allan Lane
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Patent number: 10026847Abstract: In a semiconductor element including an oxide semiconductor film as an active layer, stable electrical characteristics are achieved. A semiconductor element includes a base film which is an oxide film at least a surface of which has crystallinity; an oxide semiconductor film having crystallinity over the base film; a gate insulating film over the oxide semiconductor film; a gate electrode overlapping with at least the oxide semiconductor film, over the gate insulating film; and a source electrode and a drain electrode which are electrically connected to the oxide semiconductor film. The base film is a film containing indium and zinc. With the structure, a state of crystals in the oxide semiconductor film reflects that in the base film; thus, the oxide semiconductor film can have crystallinity in a large region in the thickness direction. Accordingly, the electrical characteristics of the semiconductor element including the film can be made stable.Type: GrantFiled: November 13, 2012Date of Patent: July 17, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Tatsuya Honda, Suzunosuke Hiraishi, Hiroshi Kanemura, Masashi Oota
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Patent number: 10014346Abstract: According to one embodiment, a semiconductor memory device includes a first interconnect, a second interconnect, a first fringe and a second fringe. The first interconnect is connected to a first memory cell. The second interconnect is connected to a second memory cell and is arranged at a first interval from the first interconnect in a first direction. The first fringe is formed on one end of the first interconnect. The second fringe is formed on one end of the second interconnect. The first fringe and the second fringe are arranged at the first interval in a second direction orthogonal to the first direction.Type: GrantFiled: February 23, 2011Date of Patent: July 3, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventor: Hiroyuki Nitta
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Patent number: 10008574Abstract: A gate structure includes at least one spacer defining a gate region over a semiconductor substrate, a gate dielectric layer disposed on the gate region over the semiconductor substrate, a first work function metal layer disposed over the gate dielectric layer and lining a bottom surface of an inner sidewall of the spacer, and a filling metal partially wrapped by the first work function metal layer. The filling metal includes a first portion and a second portion, wherein the first portion is between the second portion and the semiconductor substrate, and the second portion is wider than the first portion.Type: GrantFiled: October 13, 2016Date of Patent: June 26, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Bo-Wen Hsieh, Wen-Jia Hsieh, Yi-Chun Lo
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Patent number: 9997550Abstract: A photodetector is formed in a silicon-on-insulator (SOI) type semiconductor layer. The photodetector includes a first region and a second region of a first conductivity type separated from each other by a central region of a second conductivity type so as to define a phototransistor. A transverse surface of the semiconductor layer is configured to receive an illumination. The transverse surface extends orthogonally to an upper surface of the central region.Type: GrantFiled: February 20, 2015Date of Patent: June 12, 2018Assignee: STMICROELECTRONICS SAInventor: Bruno Rauber
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Patent number: 9924283Abstract: This application relates to a systems and methods for enhanced dynamics processing of streaming audio by source separation and remixing for hearing assistance devices, according to one example. In one embodiment, an external streaming audio device processes sources isolated from an audio signal using source separation, and mixes the resulting signals back into the unprocessed audio signal to enhance individual sources while minimizing audible artifacts. Variations of the present system use source separation in a side chain to guide processing of a composite audio signal.Type: GrantFiled: October 31, 2016Date of Patent: March 20, 2018Assignee: Starkey Laboratories, Inc.Inventor: Kelly Fitz
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Patent number: 9831382Abstract: A solution for fabricating a semiconductor structure is provided. The semiconductor structure includes a plurality of semiconductor layers grown over a substrate using a set of epitaxial growth periods. During each epitaxial growth period, a first semiconductor layer having one of: a tensile stress or a compressive stress is grown followed by growth of a second semiconductor layer having the other of: the tensile stress or the compressive stress directly on the first semiconductor layer.Type: GrantFiled: December 3, 2012Date of Patent: November 28, 2017Assignee: Sensor Electronic Technology, Inc.Inventors: Rakesh Jain, Wenhong Sun, Jinwei Yang, Maxim S. Shatalov, Alexander Dobrinsky, Remigijus Gaska, Michael Shur
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Patent number: 9721874Abstract: Pre-encapsulated lead frames suitable for use in microelectronic device packages are disclosed. Individual lead frames can include a set of multiple lead fingers arranged side by side with neighboring lead fingers spaced apart from each other by a corresponding gap. An encapsulating compound at least partially encapsulates the set of lead fingers without encapsulating a microelectronic device. The encapsulating compound can generally fill the plurality of gaps between two adjacent lead fingers.Type: GrantFiled: January 22, 2013Date of Patent: August 1, 2017Assignee: Micron Technology, Inc.Inventors: Ai Chie Wang, Choon Kuan Lee, Chin Hui Chong, Wuu Yean Tay
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Patent number: 9704944Abstract: An integrated circuit contains three thin film resistors over a dielectric layer. The first resistor body includes only a bottom thin film layer and the first resistor heads include the bottom thin film layer, a middle thin film layer and a top thin film layer. The second resistor body and heads include all three thin film layers. The third resistor body does not include the middle thin film layer. The three resistors are formed using two etch masks.Type: GrantFiled: February 28, 2013Date of Patent: July 11, 2017Assignee: TEXAS INSTRUMENTS DEUTSCHLAND GMBHInventors: Christoph Dirnecker, Karsten Spinger, Franz Stingl
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Patent number: 9520486Abstract: An apparatus including an electrostatic discharge (ESD) protection device comprising a semiconductor having first, second and third regions arranged to form a transistor, wherein the first region is doped with a first impurity of a first conductivity type and is separated from the second region which is doped with a second impurity of a second conductivity type opposite the first type, and wherein a dimensional constraint of the regions defines an operational threshold of the ESD protection device. In one example, the separation between a collector and an emitter of a bipolar transistor defines a trigger voltage to cause the electrostatic discharge protection device to become conducting. In another example, a width of a bipolar transistor base controls a holding voltage of the electrostatic discharge protection device.Type: GrantFiled: November 4, 2009Date of Patent: December 13, 2016Assignee: Analog Devices, Inc.Inventors: Edward John Coyne, Patrick Martin McGuinness, Paul Malachy Daly, Bernard Patrick Stenson, David J. Clarke, Andrew David Bain, William Allan Lane
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Patent number: 9496460Abstract: Provided are a light emitting device, an electrode structure, a light emitting device package, and a lighting system. The light emitting device includes a light emitting structure layer comprising a first semiconductor layer, a second semiconductor layer, and an active layer. An electrode disposed on a top surface of the first semiconductor layer, a first layer includes a transmittive oxide material between the top surface of the first semiconductor layer and the electrode, and a second layer disposed is disposed between the first layer and the electrode, wherein the first layer is formed in a different material from the second layer, wherein the electrode comprises a lower portion connected to the first semiconductor layer and an upper portion on a top surface of the second layer.Type: GrantFiled: October 16, 2013Date of Patent: November 15, 2016Assignee: LG Innotek Co., Ltd.Inventors: Kwang Ki Choi, Hwan Hee Jeong, Sang Youl Lee, June O Song
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Patent number: 9485589Abstract: This application relates to a systems and methods for enhanced dynamics processing of streaming audio by source separation and remixing for hearing assistance devices, according to one example. In one embodiment, an external streaming audio device processes sources isolated from an audio signal using source separation, and mixes the resulting signals back into the unprocessed audio signal to enhance individual sources while minimizing audible artifacts. Variations of the present system use source separation in a side chain to guide processing of a composite audio signal.Type: GrantFiled: December 21, 2012Date of Patent: November 1, 2016Assignee: Starkey Laboratories, Inc.Inventor: Kelly Fitz
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Patent number: 9472684Abstract: A gallium nitride (GaN)-based junction field-effect transistor (JFET) can include a GaN drain region having a top surface extending in a lateral dimension, a source region, and a GaN channel region of a first conductivity type coupled between the source region and the GaN drain region and operable to conduct electrical current between the source region and the GaN drain region. The JFET can also include a blocking layer disposed between the source region and the GaN drain region such that the GaN channel region is operable to conduct the electrical current substantially along the lateral dimension in a laterally-conductive region of the GaN channel region, and a GaN gate region of a second conductivity type coupled to the GaN channel region such that the laterally-conductive region of the GaN channel region is disposed between at least a portion of the blocking layer and the GaN gate region.Type: GrantFiled: November 13, 2012Date of Patent: October 18, 2016Assignee: Avogy, Inc.Inventors: Hui Nie, Andrew Edwards, Isik Kizilyalli, Dave Bour, Thomas R. Prunty
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Patent number: 9472629Abstract: A method of fabricating a single crystal gallium nitride substrate the step of cutting an ingot of single crystal gallium nitride along predetermined planes to make one or more signal crystal gallium nitride substrates. The ingot of single crystal gallium nitride is grown by vapor phase epitaxy in a direction of a predetermined axis. Each predetermined plane is inclined to the predetermined axis. Each substrate has a minor polished primary surface. The primary surface has a first area and a second area. The first area is between an edge of the substrate and a line 3 millimeter away from the edge. The first area surrounds the second area. An qaxis perpendicular to the primary surface forms an off-angle with c-axis of the substrate. The off-angle takes a minimum value at a first position in the first area of the primary surface.Type: GrantFiled: November 30, 2015Date of Patent: October 18, 2016Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventor: Masaki Ueno
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Patent number: 9370047Abstract: Apparatuses and techniques relating to a resistive heating device are provided.Type: GrantFiled: October 15, 2013Date of Patent: June 14, 2016Assignee: KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATIONInventor: Kwangyeol Lee
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Patent number: 9357956Abstract: A spectroscopic sensor has plural angle limiting filters that limit incident angles of incident lights, plural light band-pass filters that transmit specific wavelengths, and plural photodiodes to which corresponding transmitted lights are input. The spectroscopic sensor is a semiconductor device in which the angle limiting filters, the light band-pass filters, and the photodiodes are integrated, and, assuming that the surface on which impurity regions for the photodiodes are formed is a front surface of a semiconductor substrate, holes for receiving lights are formed in the impurity regions from the rear surface side.Type: GrantFiled: March 2, 2011Date of Patent: June 7, 2016Assignee: SEIKO EPSON CORPORATIONInventors: Akira Uematsu, Noriyuki Nakamura, Akira Komatsu, Kunihiko Yano
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Patent number: 9362331Abstract: A method for forming image sensors includes providing a substrate and forming a plurality of photo diode regions, each of the photo diode regions being spatially disposed on the substrate. The method also includes forming an interlayer dielectric layer overlying the plurality of photo diode regions, forming a shielding layer formed overlying the interlayer dielectric layer, and applying a silicon dioxide bearing material overlying the shielding layer. The method further includes etching portions of the silicon dioxide bearing material to form a plurality of first lens structures, and continuing to form each of the plurality of first lens structures to provide a plurality of finished lens structures.Type: GrantFiled: April 1, 2014Date of Patent: June 7, 2016Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Herb He Huang, Mieno Fumitake
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Patent number: 9356094Abstract: A method for making a silicon layer extending on an insulation layer, including the steps of forming a silicon-germanium layer on at least a portion of a silicon wafer; transforming portions of the silicon-germanium layer into porous silicon pads; growing a monocrystalline silicon layer on the silicon-germanium layer and on the porous silicon pads; removing the silicon-germanium layer; oxidizing the porous silicon pads; and depositing an insulation material on the silicon layer.Type: GrantFiled: May 31, 2013Date of Patent: May 31, 2016Assignee: STMicroelectronics (Crolles 2) SASInventors: Aomar Halimaoui, Daniel Bensahel
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Patent number: 9356033Abstract: Nonvolatile memory devices include a string of nonvolatile memory cells on a substrate. This string of nonvolatile memory cells includes a first vertical stack of nonvolatile memory cells on the substrate and a string selection transistor on the first vertical stack of nonvolatile memory cells. A second vertical stack of nonvolatile memory cells is also provided on the substrate and a ground selection transistor is provided on the second vertical stack of nonvolatile memory cells. This second vertical stack of nonvolatile memory cells is provided adjacent the first vertical stack of nonvolatile memory cells. A conjunction doped semiconductor region is provided in the substrate. This conjunction doped region electrically connects the first vertical stack of nonvolatile memory cells in series with the second vertical stack of nonvolatile memory cells so that these stacks can operate as a single NAND-type string of memory cells.Type: GrantFiled: July 28, 2015Date of Patent: May 31, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Hoon Son, Jung Ho Kim, Seungjae Baik, Myoungbum Lee, Kihyun Hwang