Abstract: An optoelectronic semiconductor chip, the latter includes a carrier and a semiconductor layer sequence grown on the carrier. The semiconductor layer sequence is based on a nitride-compound semiconductor material and contains at least one active zone for generating electromagnetic radiation and at least one waveguide layer, which indirectly or directly adjoins the active zone. A waveguide being formed. In addition, the semiconductor layer sequence includes a p-cladding layer adjoining the waveguide layer on a p-doped side and/or an n-cladding layer on an n-doped side of the active zone. The waveguide layer indirectly or directly adjoins the cladding layer. An effective refractive index of a mode guided in the waveguide is in this case greater than a refractive index of the carrier.

Abstract: The present invention introduces the novel, improved design approach of the semiconductor devices that utilize the effect of carrier recombination, for example, to produce the electromagnetic radiation. The approach is based on the separate control over the injection of the electrons and holes into the active region of the device. As a result, better recombination efficiencies can be achieved, and the effect of the wavelength shift of the produced radiation can be eliminated. The devices according to the present invention outperform existing solid state light and electromagnetic radiation sources and can be used in any applications where solid state light sources are currently involved, as well as any applications future discovered.

Abstract: Prepared is an n? type semiconductor substrate 1 having a first principal surface 1a and a second principal surface 1b opposed to each other, and having a p+ type semiconductor region 3 formed on the first principal surface 1a side. At least a region opposed to the p+ type semiconductor region 3 in the second principal surface 1b of the n? type semiconductor substrate 1 is irradiated with a pulsed laser beam to form an irregular asperity 10. After formation of the irregular asperity 10, an accumulation layer 11 with an impurity concentration higher than that of the n? type semiconductor substrate 1 is formed on the second principal surface 1b side of the n type semiconductor substrate 1. After formation of the accumulation layer 11, the n? type semiconductor substrate 1 is subjected to a thermal treatment.

Abstract: A semiconductor element of the electric circuit includes a semiconductor layer over a gate electrode. The semiconductor layer of the semiconductor element is formed of a layer including polycrystalline silicon which is obtained by crystallizing amorphous silicon by heat treatment or laser irradiation, over a substrate. The obtained layer including polycrystalline silicon is also used for a structure layer such as a movable electrode of a structure body. Therefore, the structure body and the electric circuit for controlling the structure body can be formed over one substrate. As a result, a micromachine can be miniaturized. Further, assembly and packaging are unnecessary, so that manufacturing cost can be reduced.

Abstract: An image pickup device, wherein a part of the carriers overflowing from the photoelectric conversion unit for a period of photoelectrically generating and accumulating the carriers may be flowed into the floating diffusion region, and a pixel signal generating unit generating a pixel signal according to the carriers stored in the photoelectric conversion unit and the carriers having overflowed into the floating diffusion region, is provided. The expansion of a dynamic range and the improvement of an image quality can be provided by controlling a ratio of the carriers flowing into the floating diffusion region to the carriers overflowing from such a photoelectric conversion unit at high accuracy.

Abstract: An apparatus comprises a processor configured to receive a first audio signal and first location data, the first location data relating to a location of a source of the first audio signal; receive a second audio signal and second location data, the second location data relating to a location of a source of the second audio signal; receive selected location data relating to a selected location; and generate a multichannel signal in dependence on the first and second audio signals, the first and second location data and the selected location data.

Abstract: A semiconductor structure, comprising: a substrate; a seed layer over an upper surface of the substrate; a semiconductor layer disposed over the seed layer; a transistor device in the semiconductor layer; wherein the substrate has an aperture therein, such aperture extending from a bottom surface of the substrate and terminating on a bottom surface of the seed layer; and an opto-electric structure disposed on the bottom surface of the seed layer.

Abstract: Inductors and methods for integrated circuits that result in inductors of a size compatible with integrated circuits, allowing the fabrication of inductors, with or without additional circuitry on a first wafer and the bonding of that wafer to a second wafer without wasting of wafer area. The inductors in the first wafer are comprised of coils formed by conductors at each surface of the first wafer coupled to conductors in holes passing through the first wafer. Various embodiments are disclosed.

Abstract: An LED module includes at least two LED package units and at least one connecting unit. Each LED package unit includes at least one first engaging portion, at least one first conductive portion, and at least one LED chip connected electrically to the first engaging portion. The connecting unit includes at least two second engaging portions, and at least one second conductive portion having two opposite end sections extending respectively to the second engaging portions. When the second engaging portions of the connecting unit engaged with the first engaging portions of the LED package units, respectively, the end sections of the second conductive portion contact electrically and respectively the corresponding first conductive portions so as to connect electrically the LED chips of the LED package units.

Abstract: Provided is a power semiconductor device including: a power semiconductor element; a metal block as a first metal block that is connected to the power semiconductor element through an upper surface electrode pattern as a first upper surface electrode pattern selectively formed on an upper surface of the power semiconductor element; and a mold resin filled so as to cover the power semiconductor element and the metal block, wherein an upper surface of the metal block is exposed from a surface of the mold resin.

Abstract: The invention is an optoelectronic device comprising an active portion which converts light to electricity or converts electricity to light, the active portion having a front side for the transmittal of the light and a back side opposite from the front side, at least two electrical leads to the active portion to convey electricity to or from the active portion, an enclosure surrounding the active portion and through which the at least two electrical leads pass wherein the hermetically sealed enclosure comprises at the front side of the active portion a barrier material which allows for transmittal of light, one or more getter materials disposed so as to not impede the transmission of light to or from the active portion, and a contiguous gap pathway to the getter material which pathway is disposed between the active portion and the barrier material.

Abstract: An exemplary thin film transistor array substrate (200) includes a substrate (210) and a gate electrode (220) formed on the substrate. The gate electrode includes an adhesive layer (226) formed on the substrate, a conductive layer (224) formed on the adhesive layer and a barrier layer (222) formed on the conductive layer, the adhesive layer and the barrier layer both have sandwich structures. A central core of the adhesive layer, the conductive layer, and a central core of the barrier layer are made of a same material.

Abstract: A first select transistor is formed on a semiconductor substrate. Memory cell transistors are stacked on the first select transistor and connected in series. A second select transistor is formed on the memory cell transistors. The memory cell transistors include a tapered semiconductor pillar which increases in diameter from the first select transistor toward the second select transistor, a tunnel dielectric film formed on the side surface of the semiconductor pillar, a charge storage layer which is formed on the side surface of the tunnel dielectric film and which increases in charge trap density from the first select transistor side toward the second select transistor side, a block dielectric film formed on the side surface of the charge storage layer, and conductor films which are formed on the side surface of the block dielectric film and which serve as gate electrodes.

Abstract: The present invention provides a method of forming a transistor. The method includes forming a first layer of a first semiconductor material above an insulation layer. The first semiconductor material is selected to provide high mobility to a first carrier type. The method also includes forming a second layer of a second semiconductor material above the first layer of semiconductor material. The second semiconductor material is selected to provide high mobility to a second carrier type opposite the first carrier type. The method further includes forming a first masking layer adjacent the second layer and etching the second layer through the first masking layer to form at least one feature in the second layer. Each feature in the second layer forms an inverted-T shape with a portion of the second layer.

Abstract: An integrated circuit includes a graphene layer, the graphene layer comprising a region of undoped graphene, the undoped graphene comprising a channel of a transistor, and a region of doped graphene, the doped graphene comprising a contact of the transistor; and a gate of the transistor, the gate comprising a carbon nanotube film. A method of fabricating an integrated circuit comprising graphene and carbon nanotubes, includes forming a graphene layer; doping a portion of the graphene layer, resulting in doped graphene and undoped graphene; forming a carbon nanotube film; and etching the carbon nanotube film to form a gate of a transistor, wherein the transistor further comprises a channel comprising the undoped graphene and a contact comprising the doped graphene. A transistor includes a gate, the gate comprising a carbon nanotube film; a channel, the channel comprising undoped graphene; and a contact, the contact comprising doped graphene.

Abstract: A hollow part is formed in a silicon substrate through the front and the back. A vibration electrode plate is arranged on an upper surface of the silicon substrate to cover the opening on the upper surface. A fixed electrode plate covers the upper side of the vibration electrode plate while maintaining a microscopic gap with the vibration electrode plate, where the peripheral part is fixed to the upper surface of the silicon substrate. The fixed electrode plate has the portion facing the upper surface of the silicon substrate through a space supported by a side wall portion arranged on an inner edge of the portion fixed to the upper surface of the silicon substrate without interposing a space. The outer surface of the side wall portion of the fixed electrode plate is covered by a reinforcement film made of metal such as Au, Cr, and Pt.

Abstract: An integrated circuit includes a graphene layer, the graphene layer comprising a region of undoped graphene, the undoped graphene comprising a channel of a transistor, and a region of doped graphene, the doped graphene comprising a contact of the transistor; and a gate of the transistor, the gate comprising a carbon nanotube film. A method of fabricating an integrated circuit comprising graphene and carbon nanotubes, includes forming a graphene layer; doping a portion of the graphene layer, resulting in doped graphene and undoped graphene; forming a carbon nanotube film; and etching the carbon nanotube film to form a gate of a transistor, wherein the transistor further comprises a channel comprising the undoped graphene and a contact comprising the doped graphene. A transistor includes a gate, the gate comprising a carbon nanotube film; a channel, the channel comprising undoped graphene; and a contact, the contact comprising doped graphene.

Abstract: To improve jump characteristic of BaTiO3—(Bi1/2Na1/2)TiO3 material. There is provided a process for producing a semiconductive porcelain composition in which a part of Ba is substituted with Bi—Na, the process including a step of preparing a (BaQ)TiO3 calcined powder (in which Q is a semiconductor dopant), a step of preparing a (BiNa)TiO3 calcined powder, a step of mixing the (BaQ)TiO3 calcined powder and the (BiNa)TiO3 calcined powder, a step of molding and sintering the mixed calcined powder, and a step of heat-treating the obtained sintered body at 600° C. or lower; and a PCT heater employing the element prepared by the above steps.

Abstract: A solid-state imaging device includes: a substrate including a plurality of light receiving sections; and a color filter including a guided-mode resonant grating provided immediately above each of the plurality of light receiving sections, at least one of an upper surface and a lower surface of the guided-mode resonant grating being covered with a layer having a lower refractive index than the guided-mode resonant grating.

Abstract: An improved image sensor, e.g., CCD, CID, CMOS. The image sensor includes a substrate, e.g., silicon wafer. The sensor also includes a plurality of photo diode regions, where each of the photo diode regions is spatially disposed on the substrate. The sensor has an interlayer dielectric layer overlying the plurality of photo diode regions and a shielding layer formed overlying the interlayer dielectric layer. A silicon dioxide bearing material is overlying the shielding layer. A plurality of lens structures are formed on the silicon dioxide bearing material. The sensor also has a color filter layer overlying the lens structures and a plurality of second lens structures overlying the color filter layer according to a preferred embodiment.