Patents Examined by Lynne A. Gurley
  • Patent number: 10998331
    Abstract: A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips located over a substrate and laterally spaced apart among one another by line trenches. The line trenches laterally extend along a first horizontal direction and are spaced apart along a second horizontal direction. Each line trench fill structure includes a laterally undulating dielectric rail having a laterally undulating width along the second horizontal direction and extending along the first horizontal direction and a row of memory stack structures located at neck regions of the laterally undulating dielectric rail.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: May 4, 2021
    Inventors: Fei Zhou, Yingda Dong, Raghuveer S. Makala
  • Patent number: 10985303
    Abstract: A thermally efficient, cost efficient and compact LED device having an LED module and a circuit board. The LED module having an LED substrate and an LED chip mounted on a mounting surface of the LED substrate. The circuit board is composed of a circuit board substrate and has a plurality of conductive tracks on a surface of the circuit board substrate. The LED substrate is embedded in the circuit board substrate.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: April 20, 2021
    Assignee: Lumileds LLC
    Inventor: Robert Derix
  • Patent number: 10741693
    Abstract: A thin film transistor includes a gate electrode, an active layer formed of oxide semiconductor material on a substrate, and a gate insulation layer therebetween. The active layer includes a channel region corresponding to the gate electrode, a source region at one side of the channel region, and a drain region at the other side of the channel region. The source region includes a first upper portion and the drain region includes a second upper portion that includes the oxide semiconductor material and Si.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: August 11, 2020
    Assignee: LG Display Co., Ltd.
    Inventor: Ju-Heyuck Baeck
  • Patent number: 10741687
    Abstract: A trench DMOS transistor with a very low on-state drain-to-source resistance and a high gate-to-drain charge includes one or more floating islands that lie between the gate and drain to reduce the charge coupling between the gate and drain, and effectively lower the gate-to-drain capacitance.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: August 11, 2020
    Inventors: Yaojian Leng, Richard Foote, Steven J. Adler
  • Patent number: 10741548
    Abstract: A semiconductor device includes a vertical protection device having a thyristor and a lateral trigger element disposed in a substrate. The lateral trigger element is for triggering the vertical protection device.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: August 11, 2020
    Inventors: Vadim Valentinovic Vendt, Joost Willemen, Andre Schmenn, Damian Sojka
  • Patent number: 10737931
    Abstract: A semiconductor structure includes a first device and a second device. The first device includes a plate including a plurality of apertures; a membrane disposed opposite to the plate and including a plurality of corrugations, and a conductive plug extending through the plate and the membrane. The second device includes a substrate and a bond pad disposed over the substrate, wherein the conductive plug is bonded with the bond pad to integrate the first device with the second device, and the plate includes a semiconductive member and a tensile member, and the semiconductive member is disposed within the tensile member.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: August 11, 2020
    Inventors: Yi-Hsien Chang, Chun-Ren Cheng, Wei-Cheng Shen, Wen-Chien Chen
  • Patent number: 10741688
    Abstract: The present disclosure provides many different embodiments of an IC device. The IC device includes a gate stack disposed over a surface of a substrate and a spacer disposed along a sidewall of the gate stack. The spacer has a tapered edge that faces the surface of the substrate while tapering toward the gate stack. Therefore the tapered edge has an angle with respect to the surface of the substrate.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: August 11, 2020
    Inventors: Shin-Jiun Kuang, Tsung-Hsing Yu, Yi-Ming Sheu
  • Patent number: 10714464
    Abstract: Selective transfer of dies including semiconductor devices to a target substrate can be performed employing local laser irradiation. Coining of at least one set of solder material portions can be employed to provide a planar surface-to-surface contact and to facilitate bonding of adjoining pairs of bond structures. Laser irradiation on the solder material portions can be employed to sequentially bond selected pairs of mated bonding structures, while preventing bonding of devices not to be transferred to the target substrate. Additional laser irradiation can be employed to selectively detach bonded devices, while not detaching devices that are not bonded to the target substrate. The transferred devices can be pressed against the target substrate during a second reflow process so that the top surfaces of the transferred devices can be coplanar. Wetting layers of different sizes can be employed to provide a trapezoidal vertical cross-sectional profile for reflowed solder material portions.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: July 14, 2020
    Assignee: GLO AB
    Inventors: Anusha Pokhriyal, Sharon N. Farrens, Timothy Gallagher
  • Patent number: 10707189
    Abstract: A light-emitting device is provided whose color mixing property and light emission efficiency are improved, while white light with high color rendering performance is ensured by means of four kinds of LED elements emitting red, green, blue, and white light respectively.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: July 7, 2020
    Assignees: Citizen Electronics Co., Ltd., Citizen Watch Co., Ltd.
    Inventors: Masahiko Hamada, Hirohiko Ishii
  • Patent number: 10460943
    Abstract: Some embodiments include an integrated structure having a gallium-containing material between a charge-storage region and a semiconductor-containing channel region. Some embodiments include an integrated structure having a charge-storage region under a conductive gate, a tunneling region under the charge-storage region, and a semiconductor-containing channel region under the tunneling region. The tunneling region includes at least one dielectric material directly adjacent a gallium-containing material. Some embodiments include an integrated structure having a charge-trapping region under a conductive gate, a first oxide under the charge-storage region, a gallium-containing material under the first oxide, a second oxide under the gallium-containing material, and a semiconductor-containing channel region under the second oxide.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: October 29, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Chris M. Carlson
  • Patent number: 10388863
    Abstract: A 3D integrated circuit device, including: a first transistor; a second transistor; and a third transistor, where the third transistor is overlaying the second transistor and is controlled by a third control line, where the second transistor is overlaying the first transistor and is controlled by a second control line, where the first transistor is part of a control circuit controlling the second control line and third control line, and where the first transistor, the second transistor and the third transistor are all aligned to each other with less than 100 nm misalignment.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: August 20, 2019
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Patent number: 10355179
    Abstract: An LED package structure includes a carrier mounted with a plurality of LED chips, a first glue-layer, a second glue-layer and an encapsulation resin filled within the first and the second glue-layers. The first glue-layer is formed on a top surface of the carrier and has a thin-film structure which is substantially flat on a top surface thereof. The second glue-layer is stacked on the first glue-layer. The second glue-layer has a height higher than that of the first glue-layer. The second glue-layer has a volume greater than that of the first glue-layer. The present invention also provides a method of LED package structure to stably produce a dam structure with uniform shape and high ratio of height/width.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: July 16, 2019
    Inventor: Kuo-Ming Chiu
  • Patent number: 10204980
    Abstract: A semiconductor device may include an element region and a peripheral voltage withstanding region. The peripheral voltage withstanding region includes inner circumferential guard rings; and outer circumferential guard rings having a width narrower than a width of the inner circumferential guard rings. An interval between the inner circumferential guard rings is narrower than an interval between the outer circumferential guard rings. Each of the inner circumferential guard rings includes a first high concentration region and a first low concentration region. Each of the outer circumferential guard rings includes a second high concentration region and a second low concentration region. A width of a part of each first low concentration region that is exposed on a front surface of the semiconductor device is wider than a width of a part of each second low concentration region that is exposed on the front surface.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: February 12, 2019
    Inventors: Yoshifumi Yasuda, Tatsuji Nagaoka, Yasushi Urakami, Sachiko Aoi
  • Patent number: 10170380
    Abstract: An array substrate and a display device are provided. The array substrate includes a display region and a peripheral circuit region, wherein a first gate line, a first data line and a pixel region are arranged in the display region; the pixel region includes a first pixel electrode and a thin film transistor, and the thin film transistor includes a first gate electrode, a first source electrode and a first drain electrode; the peripheral circuit region is provided with at least one test unit including: a second gate line; a second data line; a second testing pixel electrode; and a second testing thin film transistor. The second testing thin film transistor includes a second gate electrode, a second source electrode and a second drain electrode, wherein the second gate electrode, the second source electrode and the second drain electrode are provided with test ports exposed outside.
    Type: Grant
    Filed: December 10, 2013
    Date of Patent: January 1, 2019
    Inventors: Ming Zhang, Guoqi Mao, Zhaohui Hao, Woong Sun Yoon
  • Patent number: 10128371
    Abstract: A method for forming a semiconductor device is disclosed. The method includes providing a semiconductor substrate. The method also includes epitaxially growing on the semiconductor substrate a first part of a III-V semiconductor nanostructure. The method further includes covering the first part of the III-V semiconductor nanostructure with a layer of a first material. Additionally, the method includes removing a top portion of the layer of the first material. Still further, the method includes epitaxially growing on the first part of the III-V semiconductor nanostructure a second part of the III-V semiconductor nanostructure. The method additionally includes covering the second part of the III-V semiconductor nanostructure with a layer of a second material. The second material is different from the first material. Even further, the method includes removing a top portion of the layer of the second material.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: November 13, 2018
    Assignee: IMEC VZW
    Inventors: Boon Teik Chan, Clement Merckling, Zheng Tao
  • Patent number: 10121938
    Abstract: A light source module is provided. The light source module includes a flexible printed circuit board, plural light-emitting diodes and plural first light-absorbing portions. The flexible printed circuit board has a first edge and a second edge opposite to the first edge. The light-emitting diodes are disposed on the flexible printed circuit board near the first edge. The first light-absorbing portions are disposed on the flexible printed circuit board near the second edge, in which the first light-absorbing portions are alternately arranged with the light-emitting diodes.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: November 6, 2018
    Assignee: Radiant Opto-Electronics Corporation
    Inventors: Chia-Yin Chang, Chin-Ting Weng
  • Patent number: 10121861
    Abstract: A nanowire device of the present description may be produced with the incorporation of at least one hardmask during the fabrication of at least one nanowire transistor in order to assist in protecting an uppermost channel nanowire from damage that may result from fabrication processes, such as those used in a replacement metal gate process and/or the nanowire release process. The use of at least one hardmask may result in a substantially damage free uppermost channel nanowire in a multi-stacked nanowire transistor, which may improve the uniformity of the channel nanowires and the reliability of the overall multi-stacked nanowire transistor.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 6, 2018
    Assignee: Intel Corporation
    Inventors: Seung Hoon Sung, Seiyon Kim, Kelin Kuhn, Willy Rachmady, Jack Kavalieros
  • Patent number: 10043850
    Abstract: An HV-LED module having 3D light-emitting structure and a method for manufacturing the HV-LED module are disclosed. The HV-LED module has at least two stacked parts of substage LEDs that each have an independent light-emitting structure and are bonded in a staggered pattern, and the substage LEDs are connected in series to form the 3D light-emitting structure, thereby significantly increasing light-emitting power per unit area, downsizing a high-voltage chip module using it by nearly two times, and effectively reducing packaging costs for the HV-LED module.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: August 7, 2018
    Assignee: Xiamen Changelight Co., Ltd.
    Inventors: Zhiwei Lin, Kaixuan Chen, Yong Zhang, Xiangjing Zhuo, Wei Jiang, Tianzu Fang, Yinqiao Zhang, Xiangwu Wang
  • Patent number: 10043792
    Abstract: An apparatus including an electrostatic discharge (ESD) protection device comprising a semiconductor having first, second and third regions arranged to form a transistor, wherein the first region is doped with a first impurity of a first conductivity type and is separated from the second region which is doped with a second impurity of a second conductivity type opposite the first type, and wherein a dimensional constraint of the regions defines an operational threshold of the ESD protection device. In one example, the separation between a collector and an emitter of a bipolar transistor defines a trigger voltage to cause the electrostatic discharge protection device to become conducting. In another example, a width of a bipolar transistor base controls a holding voltage of the electrostatic discharge protection device.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: August 7, 2018
    Assignee: Analog Devices, Inc.
    Inventors: Edward John Coyne, Patrick Martin McGuinness, Paul Malachy Daly, Bernard Patrick Stenson, David J. Clarke, Andrew David Bain, William Allan Lane
  • Patent number: 10026847
    Abstract: In a semiconductor element including an oxide semiconductor film as an active layer, stable electrical characteristics are achieved. A semiconductor element includes a base film which is an oxide film at least a surface of which has crystallinity; an oxide semiconductor film having crystallinity over the base film; a gate insulating film over the oxide semiconductor film; a gate electrode overlapping with at least the oxide semiconductor film, over the gate insulating film; and a source electrode and a drain electrode which are electrically connected to the oxide semiconductor film. The base film is a film containing indium and zinc. With the structure, a state of crystals in the oxide semiconductor film reflects that in the base film; thus, the oxide semiconductor film can have crystallinity in a large region in the thickness direction. Accordingly, the electrical characteristics of the semiconductor element including the film can be made stable.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: July 17, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Tatsuya Honda, Suzunosuke Hiraishi, Hiroshi Kanemura, Masashi Oota