Abstract: The invention concerns a method and a system enabling the customers (11) of a bank or an insurance company (12), remotely located, to accede safely and rapidly, by means of a microphone (17) connected to a communication network (15), to the services offered by this bank or insurance company (12).

Abstract: A method of computing and verifying an authorization code for a transaction. The method includes creating an algebraic formula and storing the formula in a validation unit and a calculating apparatus. A calculation is made by entering values for variables of the formula into the calculating apparatus, which substitutes the values for the variables into the algebraic formula to calculate a value for an authorization code. The variables and calculated value for the authorization code are sent to the validation unit, which calculates the authorization code and determines a match between the values for the variables as determined by the calculating apparatus and the values as verified by the validation unit. The validation unit allows payment authorization only if a match exists between the values for the variables as determined by the calculating apparatus and as verified by the validation unit.

Abstract: A digital evidence system is disclosed. According to one embodiment, the digital evidence system records pertinent screen activities such as data entry into an electronic form, verification of a data transfer and a purchase order by capturing images of displayed web pages requiring interactions from the user. The captured images are transmitted back to the business and can be retrieved according to a query about any interaction so that the online business could determine what has happened on the user side when a transaction was engaged with the online business.

Abstract: The present invention provides a system for electronic commerce that reduces the amount of data needed to be stored on a user computer or electronic device. A bank processor stores information corresponding to coins or funds and the user device (such as a payer or merchant processor) needs to only store a single secret key needed to access the data stored in the bank's memory. The user's device can be a smart card since only a minimal amount of data needs to be stored on the user's device. The bank processor of the present invention may hold disposable anonymous accounts in a bank memory. When a coin is spent, the corresponding account is deleted from the bank's memory and a new account is created which corresponds to a new coin. This completes a payment from a payer processor to a merchant processor. The new account is the merchant's account. This implementation avoids the threat of computer virus attacks since a smart card is far less susceptible to these.

Abstract: A recording medium such as an optical disk has a write-once recording area in which information can be recorded once and cannot be rewritten. The write-once recording area is provided with a billing information recording area in which billing information is sequentially recorded a single time. With this arrangement, it is possible to effectively prevent the unauthorized use of the medium when carrying out off-line billing processing.

Abstract: A pulse interference canceler cancels pulse interference signals by normaing the signals and comparing in time the normalized signals to each other. An overlap of the normalized signals indicates that both channels of the pulse receiver received transmissions simultaneously or near simultaneously, thereby indicating interfering signals. Detection of the simultaneous or near simultaneous normalized pulses generates a blanking pulse that suppresses any output pulses corresponding to the received interfering signals.

Abstract: A Voronoi signal constellation includes those points of a coset of a lattice .LAMBDA. that lie within a Voronoi region of a sublattice .LAMBDA.' of .LAMBDA., where .LAMBDA.' is other than a scaled version of .LAMBDA.. The Voronoi signal constellation is combined with a coset code. A method of mapping data words to Voronoi constellation points is described.

Abstract: In a data transmission system data is sent, after suitable conversion, as a ternary analog type signal. Using two-wire twisted pairs and hybrids, echo cancellation and feedback equalization are needed.Synchronization between the two ends, e.g. of a 144 Kb/sec. subscriber's loop is maintained by a low amplitude pilot tone sent with the data, and detects at the same time as the data is detected. Detection and elimination of this pilot tone use coefficient generation circuitry similar to those used in the equalizer and echo canceller.

Abstract: A modem receiver having a timing recovery circuit is disclosed. The timing recovery circuit includes circuitry for extracting timing information, multiplication circuitry responsive to the timing information for providing a clock envelope signal and processing circuitry for controlling the gain of the clock envelope signal as a function of the average power of the clock envelope signal.

Abstract: The present method is a decoding scheme for suppressing excessive amount of zeroes transmitted via a T1 line facility. Clear channel transmission capability is provided by this scheme for 32 kb/s or 64 kb/s transmission channels. This scheme provides the proper zero bit suppression for alternating mark inversion signaling (AMI). A proper AMI signal contains no more then 15 consecutive zero bit positions. In addition to meeting the AMI signaling standards, this scheme does not induce any violations of VMR (violation monitor and removal) equipment. Thus, this scheme is transparent to existing line equipment and error monitoring equipment. This scheme provides both a necessary and sufficient method for achieving the AMI signaling requirements during clear channel signaling.

Abstract: Disclosed is a digital zero-IF selectivity section circuit which operates on a recovered input signal, digitally clocked by a first clock at a rate of FS, in receiver device. The circuit uses a second clock operating at a lesser rate than the first clock to clock an N-order FIR digital filtering means to selectively band-limit the frequency spectrum of the recovered input signal. A second digital filtering means is coupled to the output of the first FIR digital filtering means. The second digital filtering means operates at a clock speed less than or equal to the second clock speed. The second digital filtering means is used to further selectively band-limit the frequency spectrum of the recovered input signal.

Abstract: A data receiving system for digital data communication described which uses asynchronous sampling and lagrangian or prolate spheroidal function interpolation on the received signal. A received analog signal is first asynchronously sampled, digitized stored in a memory and then processed using interpolation technique to recover the correct symbol timing of the symbols in the digitized data. The minimum sampling rate commensurate with channel band width is used. The correct symbol timing is continuously adjusted within certain pre-determined limits of the interpolation interval using a "jumping" algorithm which permits continuous symbol tracking. The recovered symbols are then equalized to compensate for channel distortion and decoded to give the originally encoded data. When bursts of data are being transmitted the data stored in memory is replayed to ensure that all data in the data burst is used for communication and that there is no transmission overhead requiring extra symbols for synchronization.

Abstract: A receiver is disclosed for acquiring and tracking a data signal in a highly stressed environment. The receiver comprises first and second I.F. sections, a mixer for translation from the first I.F. frequency to the second I.F. frequency, a 2 KHz bandpass filter at the second I.F. frequency, signal translator for synchronous translation of the signal at the second I.F. frequency to baseband, a digitizer for complex sampling operation on the baseband signal, a microprocessor for processing the digital samples, and a numerically controlled oscillator coupled to the mixer and controlled by the microprocessor. The microprocessor formulates matched digital discrete Fourier Transform filters which drive frequency, phase and symbol lock loops at the symbol rate. Each of the loop filters is formed by symbol-rate recursive, first-order equations.

Abstract: A burst signal generating apparatus and related method includes a modulator circuit for modulating a carrier wave of an intermediate frequency signal with a modulating signal. The output of the modulator having a carrier wave frequency is converted to a radio frequency which is amplitude controlled in response to a burst control signal. The carrier wave of the intermediate frequency is switched in response to a burst control signal. Thus, a carrier wave of the radio frequency signal has a desired envelope, permitting ready suppression of the carrier wave during pauses between burst signals.

Abstract: A filter for filtering analog or digital samples using two sections, each including a multiplier stage having a plurality of multiplier sections, each with a respective output but a common input for applying a plurality of coefficients to a sample input to the multiplier stage, and a delay and summing network comprising a plurality of delay sections and alternate summing networks connected in series, the output of one of the multiplier sections being connected to the first delay sections in the series with each output of the other multiplier sections being connected to a respective summing network, the delay and summing network of one section being interleaved in series with the delay and summing network of the other section, and further comprising means for omitting alternate samples.

Abstract: Synchronization between a transmitter and a receiver is effected by encoding and transmitting a synchronization pulse as a series of m first waveforms followed by a series of n second waveforms. The first and second waveforms are of the same duration and are transmitted in phase with each other; and m and n are positive real numbers, with m greater than one. The second waveform is different from, and preferably negatively correlated with, the first. When the receiver detects a series of first waveforms in the received signal, it locally generates a series of (either first or second) waveforms and correlates the locally-generated signal with the received signal. A change in correlation is detected as the synchronization pulse.

Abstract: Digitized FM signals are fed to a sample-and-hold circuit followed by a first sampling stage which is clocked by a second sampling signal whose frequency is an integral multiple of the frequency of a first sampling signal. The output of the first sampling stage is coupled to the input of an interpolating filter which is clocked by the second sampling signal, and whose output is sampled in a second sampling stage clocked by the second sampling signal. The output of the second sampling stage is coupled to the inputs of two zero-crossing detectors each of which drives a group-delay-controlled monostable multivibrator. The output signals of the latter are added with an average-value compensation signal in an adder whose output is sampled in a third sampling stage clocked by the second sampling signal, and fed to a digital conversion filter clocked by the first and second sampling signals and a third sampling signal.

Abstract: A synchronizer for use in synchronizing individual signal processors in a multi-channel system is disclosed. Each synchronizer has a counter for counting its associated processor's clock pulses and, upon reaching a selected count, providing a counter frame output signal at an output thereof for use by each of the other synchronizers in the system. Each synchronizer has a voter responsive to counter output signals from each of the other synchronizers, and from itself as well, at input ports thereof. Each synchronizer's voter provides a frame sync (macro sync) pulse in each counter frame after receiving a selected number of counter frame output signals from any of the synchronizers in the system.

Abstract: Echo cancellation is carried out on a received demodulated analog signal. The apparatus comprises an analog transversal filter, a computing circuit for generating the direct coefficients a1 to ar and, eventually, feedback coefficients b2 to bm of an analog transversal filter. The input of a computing circuit is connected to the input of an analog transversal filter. The computing circuit is comprised of an analog-to-digital converter, whose output is connected to a self-adaptive digital transversal filter. The values of the digital transversal filter multiplication coefficients are applied, as coefficients, to the multipliers of the analog transversal filter. The optimization criterion is that of the mean quadratic error. The convergence algorithm is that of the gradient. The iterative correction may be carried out at each step on the digital transversal filter's group of coefficients. Or, it can be carried out cyclically of each of the digital transversal filter's coefficients.

Abstract: A receiving equipment comprises a modulator, a timing extraction unit, a PLL unit, an impulse recovery unit, a fix-equalizer, and an automatic-equalizer. A timing pull-in operation is performed, in one way, by phase-rotating a timing signal of the timing extraction unit and sends the signal to the PLL unit, and in another way, by introducing an input signal of the timing extraction unit from the equalized output of the fix-equalizer.