Abstract: An emergency broadcast alert detector having a radio receiver scanning among several predetermined frequencies. The audio output of the radio receiver is connected to a noise detector that allows scanning to continue as long as noise indicative of no signal being received is present on the audio output. When the radio receiver scans to a frequency on which a broadcast is present, the lack of noise on the audio output of the receiver causes scanning to discontinue. The audio output is also connected to a tone detector that generates an alarm for a predetermined period in the even that an alert tone of a predetermined frequency is present on the audio output of the radio receiver.

Abstract: An amplitude-modulated transmitter wherein the carrier value (T) is controlled in accordance with an improved HAPUG (controlled-carrier) method. Increased energy saving with simultaneous increase of the signal-to-noise ratio at the reception site is achieved by controlling the carrier along a static characteristic (SK) which begins, with a decreasing modulation level (P), with a residual carrier value (R), drops with increasing modulation levels to a minimum carrier value (T.sub.min) and passes into an ideal carrier-control characteristic only above a first level value (P.sub.1). Additional dynamic control results in a reduction in cross-over distortions.

Abstract: There is disclosed an automatic phasing network which network receives a data signal and synchronous timing signals. Initially, these signals are in an arbitrary but fixed phase relationship to one another. The circuit establishes a fixed phase relationship between the data and timing signals with a large degree of resistance of phase jitter. In order to accomplish these results, the circuit operates to select the edge of the clock signals which is farthest from given data transitions and uses this edge to produce a data signal which is synchronized to the timing signal. The circuit provides an accurate phase relationship between the data and timing signals for various out-of-phase conditions as where the data transitions lag the rising edge of the clock by angles which vary between -45 degrees to +315 degrees.

Abstract: An interface circuit is coupled between the last stage of an FSK receiver and a limiter to provide a biasing voltage signal to the limiter. The receiver includes a power saver circuit which supplies power on an interrupted basis. The interface circuit contains maximum and minimum detectors which derive and hold voltages corresponding to the maximum and minimum values of the discriminated signal from the receiver. These maximum and minimum corresponding voltages are averaged in a predetermined manner to provide the biasing voltage to the limiter. Thus, a proper bias voltage level can be accurately and quickly determined, and supplied to the limiter when power is supplied.

Abstract: A duplex speech transmission method is disclosed wherein a limited bandwidth transmission channel is divided in a plurality of successive time slots, alternate time slots being available for each of two parties to call in Speech signals from either of the parties are divided into time segments with the time segments associated with one of said two parties being offset in time with the time segments associated with the other of said two parties. Segments of speech when present are digitised and stored in digital form. A higher rate of quantization is used when speech is present in the segments of one party and not in those of the other party, said higher rate quantized signal being transmitted in the other party's time slot and the immediately following time slot of said one party. A lower rate of quantization is used if both parties have speech in their respective segments, the lower rate quantized signals being time compressed and transmitted in their associated time slots.

Abstract: A squelch signal generator is responsive to a digital input signal (IN) which causes a display of an eye pattern in an oscillascope. The pattern has at least one eye at each time instant appearing at a predetermined period. A squelch threshold level (V.sub.S) is preselected outside of a predetermined one of uppermost and lowermost cross-points of at least one eye. The squelch comparator compares an input level of the input signal with the first squelch threshold level to produce a resultant signal which is representative of a first result of the comparison. The resultant signal is processed at each time instant by a processing circuit into a squelch signal when the input signal is classified into an undesired signal. An additional squelch threshold level may be preselected outside of the other of the uppermost and the lowermost cross-points.

Abstract: A circuit is disclosed for separating clock and data signals from a combined data-clock stream derived from a disk. The circuit includes two memories or shift registers which sample the incoming data at alternate portions of a reference clock. The outputs of the registers are applied to a decoder which identifies which of the two registers contains the data portion and which contains the clock portion with the missing clock pattern. That determination, in turn, controls the generation of the synchronization signal for the circuit and also establishes a control signal that selects data from the other of the registers.

Abstract: A radio frequency transmission system contains at least one coherently modulated information signal, for example, a T.V. signal. At a transmission, the information signal is combined with two pilot tones, F1 and F2, related by the equation F1=N/M F2, where N and M are integers. The combined signal is suppressed-carrier modulated at microwave frequencies and transmitted to a receiver. At the receiver, the signals are demodulated by a local oscillator. The two pilot tones are then separated from the information signal and are compared to each other. The local oscillator frequency is controlled in response to this comparison such that the pilot tones at the receiver bear the same relationship to each other that they had at the transmitter. When this is achieved, the local oscillator frequency is the same as the suppressed-carrier frequency and co-channel interference is prevented.

Abstract: Recovery from loss of synchronization of a synchronous serial receiver is assured by automatic reset circuitry described herein. In a synchronous serial data receiver, synchronization, data and fill characters are received from a synchronous signal transmitter. The synchronization character is provided at the beginning of each data record to establish receiver synchronization before control data is received. The fill character is used to maintain synchronization during data reception when no useful data is available for transmission. Detection of either of these characters indicates receiver synchronization with the received data. Failure to detect either of these characters during a predetermined time interval is sensed as an error indicating that the receiver has lost synchronization with the received data.

Abstract: Strong narrowband signals interfering with the reception of a desired broadband signal in systems such as spread spectrum systems are continuously suppressed by converting the received signal to a frequency-domain representation thereof wherein strong narrowband interference components appear as strong impulse components. These impulsive components are blanked or clipped at a level that is a function of the average magnitude of the input signal. Resulting suppressed frequency-domain signals are reconverted to time-domain signals that are then available for further processing by conventional broadband signal receivers.

Abstract: An encode-decoder system for generating highly accurate, coinciding synchronizing signals at each of plural separated locations; for example, a system generating start signals for a seismic data acquisition system. The system transmits psuedo random code data over selected communication link to a respective position decoder which samples the incoming code and compares it with a standard code. If there can be established a predetermined number of successive code matches, an output start signal is enabled when the code match count first peaks and then decreases.

Abstract: A method for rapidly recovering the clock from Manchester-encoded signals using simple digital techniques is provided for use in an inexpensive Manchester-encoding receiver. The received Manchester-encoded signal is monitored to determine zero-voltage crossing. At each such crossing the frequency of the recovered clock is adjusted by comparing the occurrence of the zero-crossing with respect to the midpoint of the period of the presently-generated recovered clock. Shorten, center or lengthen adjustment signals are generated as a result of this comparison which are used to shorten or lengthen, by 1/16 increments of the inter-bit period of the received data signal, the period of the next-generated recovered-clock. The method is readily implemented as a sixteen-stage programmable counter providing a phase-locked loop.

Abstract: This invention is a circuit for detecting a framing pattern consisting of a pseudo random shift register sequence. This circuit utilizes an extremely long framing pattern without either a large amount of memory or the need to receive a large number of bits in order to recognize the framing pattern. The use of lengthy framing patterns minimizes the chance of false framing caused by patterns in bit positions other than the framing bit position. In addition, the incoming data stream may be connected directly to the shift register mechanism.

Abstract: A level comparator is used to check the incoming message header pulse amplitude and if it is of a level higher than an established level a signal is transmitted to update a digital counter whose digital output is converted by a digital to analog converter to establish an increased analog reference level. If the incoming message header is lower the counter is decremented to establish a lower reference level. Then the levels of any signals present at fixed intervals after the header or sync pulse are measured and recorded. These measured levels constitute the value of correction required for subsequent pulses and are added to or subtracted from following data pulses as required.

Abstract: A circuit arranged to measure and correct for transmission line induced disturbances at discrete intervals after receipt of a header pulse by recording the presence of any voltage deviating from a set level. These levels are registered and during receipt of the data pulses are utilized at times corresponding to the relative position of the preceding data pulses to modify subsequent data bits.

Abstract: A circuit for obtaining a clock pulse synchronized to a data signal received at a receiving side, which has a plurality of clock pulses having a repetition frequency equal to that of a clock in a transmission side but being different from one another in phase. On reception of the first data bit of the received data signal, the timing of the first data bit is detected at a detection circuit in reference to the plurality of clock pulses. According to the detected timing, a selector circuit selects one of the plurality of clock pulses with a predetermined constant phase difference from the received data signal.The detection circuit comprises D-type flip-flops, and the selector circuit comprises AND gates.

Abstract: A demodulator logic for FSK signals on an RF carrier in a direct conversion radio receiver, wherein the received signals are mixed with a local oscillator to provide quadrature baseband signals, characterized in that the demodulator logic comprises two clocked D-type flip-flops, FF1,FF2 one baseband signal being applied direct to the clock input CK of one flip-flop and inverted to the clock input CK of the other flip-flop, the second baseband signal being applied to the D inputs of both flip-flops, one input Q from one flip-flop being algebraically combined with one output Q from the other flip-flop to provide a demodulator signal output of the receiver, the two flip-flop outputs being chosen so that for a given FSK value they always have the same logic value.