Abstract: A frequency synthesizer circuit operates in a time shared mode. Thus the frequency synthesizer circuit operates to transmit and/or receive a particular frequency for a chosen small amount of time and then sequentially transmits and/or receives the other frequencies for chosen small amounts of time. After all the chosen frequencies have been transmitted and/or received the synthesizer circuit will return to the first of frequency and begin to repeat the process in cyclical fashion.

Abstract: A digital data communications system transmits digital data over a telephone line using frequency multiplexing for the different channels. Each channel includes a receiver and a transmitter coupled to the telephone line at spaced points. Each transmitter includes an FSK modulator, a bandpass filter of controllable bandwidth centered about 5 kHz with its bandwidth controlled by a bandwidth select signal related to the bandwidth needed to transmit data over that channel. A mixer combines the output of the bandpass filter with a local oscillator signal of frequency related to the selected channel to provide a difference frequency signal that is applied to a lowpass filter having a cutoff at 3 kHz that is coupled to the telephone line. Each receiver includes a lowpass filter having a cutoff at 3 kHz that couples the line to a mixer.

Abstract: A receiver in a spread-spectrum communication system is adapted to receive a signal which is modulated by a binary code modulated by a binary code or a data, and includes a matched filter which detects a correlation between the received signal and a reference signal modulated by a reference code produced by a code generator. When the received code supplied from the matched filter coincides with or is slightly displaced from the reference code, a pulse is produced from a correlation spike waveform with a relatively large amplitude to extract a desired pulse from the pulse and use it to initialize the reference code generator.

Abstract: Disclosed is a wireless talking apparatus in which signal transmission is performed by utilizing an antenna and simultaneous talking can be performed. The wireless talking apparatus is constituted by a main communication device and a subsidiary communication device, and when these main and subsidiary devices are used in one-to-one correspondency, talking can be performed in a full-duplex communication mode, and in the case where a plurality of subsidiary communication devices are prepared, mutual talking can be performed also between the subsidiary communication devices and the conversation can be monitored by the main communication device.

Abstract: A receiver for measuring the amplitude of input amplitude modulated signals over an 80 dBm range and producing a digital output. The amplifier comprises a power splitter to which an input signal is applied via a limiter. First and second video detectors are coupled to the power splitter. In the case of the second video detector, an R.F. linear amplifier is connected in the signal path to provide an overall 40 dB's of gain relative to the input of the first video detector. Each video detector comprises a detector stage whose output is connected to an amplifier chain, each amplifier in the chain having a gain of 10. The outputs of the detector stage and amplifiers are quantized and applied to a logarithmic analog-to-digital converter. The outputs of the respective analog-to-digital converters are applied to a combiner.

Abstract: Method and apparatus for looping around a digital transmission line (150) at a predetermined channel unit (172) to test the line from either end of the line. Each channel unit in the line is responsive to a first and a second received control code to perform one of two operations. When the first and second received control codes are both first predetermined control codes from one end of the line, the data channel assumes a state to pass the second received first control code and any subsequently received control codes to the next channel unit. However, when the first and second received control codes are first and second predetermined control codes from the one end of the line, respectively, the data channel unit connects the transmit path from the one line end to the receive path back to the one line end, thus looping back to the digital transmission line.

Abstract: The synchronous data receiver circuit, after temporarily storing received data in a data memory having a large enough capacity to store at least two frames, detects a frame synchronization signal pattern with a pattern match circuit, then stores the message data alone of the received data in a data buffer, detects errors with a decoder and checks whether the detected frame synchronization signal pattern is the correct pattern of the frame synchronization signal or a wrong frame synchronization signal pattern contained in the message data. If it is the correct frame synchronization signal, the message data is sent to a data processing unit at the next stage or, if it is a wrong frame synchronization signal pattern, the frame synchronization signal pattern is checked again from the next data on.

Abstract: An arrangement for generating an angle-modulated carrier signal of a constant amplitude and continuous phase .phi.(t) comprises a control circuit which in response to a given number of consecutive data symbols of symbol frequency 1/T produces addresses at a clock frequency 4q/T, where q is an integer greater than 1, and further produces phase state numbers for characterizing the value modulo-2.pi. or .phi.(t) at the boundaries of the symbol intervals. Connected to the control circuit is a signal processor comprising a read-only memory for storing values representing cos .phi.(t) and sin .phi.(t) at the clock instants, which values are processed after reading to form the analog angle-modulated signal. An arrangement having a comparatively small capacity of the read-only memory is obtained by providing that storage in this read-only memory is only effected for non-decreasing phases .phi.

Abstract: A phase and gain corrector is described for a modem for receiving QAM or PSK-encoded signals. An ideal vector corresponding to the received vector is generated and the difference or error vector is resolved into a radial component in the direction of the ideal vector a tangential component. A gain corrector and a phase corrector variable are calculated from said radial and tangential components of the error vector and used to correct the gain and phase of the received signals. A secondary detector is also used to detect signals corresponding to extreme points of the signal constellation. The output of the secondary detector is used to modify the gain corrector variable thereby compensating for large gain hits.

Abstract: A clock synchronization system in a digital data switching system, such as a digital PBX. The system has a local clock generating timing signals at a frequency greater than a nominal frequency, a circuit for lowering the local clock frequency and a comparator coupled to a second clock operating substantially at the nominal frequency for activating the lowering circuit so that the local clock is synchronized with the second clock. The system is distributed by placing the local clock and the lowering frequency on the control module of the switching system and placing the comparator to one or more of the line card modules which is receiving the second clock signals. Communication between the comparator and lowering circuit may be over a single line.

Abstract: A data telecommunications system and method is provided for sending a data stream of characters between two pieces of data terminal equipment (which can be either terminals and/or computers) connected over communication lines. A modem is connected between each piece of data terminal equipment and the communication lines, and at least one of the modems is capable of operating in both a special mode which provides optimized data transmission and a normal mode which provides direct non-optimized data transmission. Upon detection of a special mode indicating character, a modem of the data telecommunication system of the present invention will establish a link under the special mode protocol. In one embodiment, when a second special character is detected by the modem, the modem is caused to operate in a normal mode. In an alternate embodiment, the modem will store characters in a special buffer memory until either the special mode-indicating character is detected or until the buffer fills.

Abstract: An equalization system wherein a signal received over a line is equalized and the quantity of equalization is compensated based on a difference, or error, between the equalized received signal and a signal which is estimated from the received signal, including a tuning device which compensates the amount of equalization by training, which precedes reception of communication data. A difference or error range which is usable for the compensation of the quantity of equalization is set up during a training sequence. The error range sequentially increases as the training sequence proceeds. Thus, decision feedback updating during the training sequence only occurs so long as the difference between the equalized received signal and a signal which is estimated from the received signal is within the error range, which is sequentially increased during a training sequence. After completion of the training sequence decision feedback updating is always allowed.

Abstract: A dynamic trunk compression system for processing digitized speech signals. The system includes a monitoring apparatus which measure current traffic intensity at the trunk. The current traffic intensity drives an algorithm that periodically estimates blocking probabilities. When the blocking probabilities fall outside of a predetermined range, the trunk is repartitioned to provide more speech channels.

Abstract: The invention relates to a device for simulating multipath interference in order that the correction stages of a radio receiver can be tested. The device includes parallel paths, simulating the multipath environment, and a pilot tone generator for introducing pilot tone into the paths. A feedback loop continuously adjusts the phase and amplitude of segments in the paths so as to cancel pilot tone from the output whereby the loop maintains the adjustment need for maximum attenuation at the frequency of the pilot tone.

Abstract: The present invention provides a data receiving apparatus constituted in such a manner that the received data is converted into a binary code and this binary code data is encoded and this encoded data is stored in a memory, whereby a large quantity of data can be stored in a memory of a small capacity. After subsequently decoding the received encoded data, this decoded data is further encoded by another encoding means and this encoded data is stored in the memory, thereby providing an efficient and economical data receiving apparatus which can smoothly perform the data processing even in the case where the transmission speed of the data and the recording speed of the recording apparatus remarkably differ.

Abstract: An arrangement for recovering a clock signal of frequency 1/T from an angle-modulated carrier signal having a modulation index m=0.5 comprises a frequency doubler, a circuit for generating a clock signal component from the frequency-doubled signal, a clock filter for selecting the generated clock signal component and a pulse shaper for producing a clock pulse signal.The arrangement produces a reliable clock signal within a very short time after the start of the signal reception, because the frequency doubler comprises a hard limiter, a first bandpass filter connected thereto and having a Q.ltoreq.10, a balanced modulator connected to the limiter and to the first bandpass filter and a second bandpass filter having a Q.ltoreq.10 tuned to twice the carrier frequency 2f.sub.c ; and because the generating circuit comprises a frequency converter for converting the frequency-doubled signal to a frequency band around a carrier frequency f.sub.

Abstract: The digital circuit extracts synchronism signals from a serial flow of coded data according to a process which uses a phaselocked loop where the different level transitions of the signal received are separately considered and a phase is determined for each type, the latter being compared with a specific reference phase, established in the initialization step. The error signal obtained from the comparison is used for correcting synchronism signal frequency.

Abstract: A transmitter for digital radio communication creates a null by balanced encoding of data modulated on an RF carrier, and inserts a calibration tone within the null. By having the calibration tone coincide in phase and frequency with the transmitted radio frequency output for coherent demodulation of data at the receiver where the tone calibration signal is extracted and used for multipath fading compensation.

Abstract: A channel unit (172) for looping around a digital transmission line (150) in response to first and second received control codes. When the first and second received control codes are both first predetermined control codes from one end of the line, the data channel assumes a state to pass the second received first control code and any subsequently received control codes to the next channel unit. However, when the first and second received control codes are first and second predetermined control codes from the one end of the line, respectively, the data channel unit connects the transmit path from the one line end to the receive path back to the one line end, thus looping back the digital transmission line.

Abstract: A decoding circuit is operative to decode a differential Manchester code consisting of four symbols "J", "K", "1" and "0" each composed of two consecutive signal elements. For detection of the symbol "J" and consequent determination of the symbol boundary, the decoding circuit has a circuit configuration which takes advantage of the fact that the symbol "K" immediately follows the symbol "J" and three consecutive signal elements, two of which are included in the symbol "J" and one of which is for a symbol immediately preceding the symbol "J", have the same polarity. To prevent an error that a second occurrence of the symbol "J" is detected after completion of detection of the symbol "J", the decoding circuit has an additional circuit configuration which inhibits the detection of the symbol "J" until the symbol "0" or the symbol "1", for example, is detected.