Patents Examined by M. Wilczewski
  • Patent number: 8445350
    Abstract: According to an embodiment of a semiconductor device and a method of manufacturing the same, buried gates are formed in a semiconductor substrate including a cell region and a peripheral region, with the cell region and the peripheral region formed to have a step therebetween. Next, a spacer is formed in a region between the cell region and the peripheral region to block an oxidation path between a gate oxide layer and another insulating layer. Embodiments may reduce damage to active regions and prevent IDD failure because a gate pattern is formed on a guard region provided at a periphery of the cell region.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: May 21, 2013
    Assignee: Hynix Semiconductor, Inc.
    Inventor: Dong Hee Han
  • Patent number: 8153459
    Abstract: An organic light emitting diode display device includes a switch TFT and a drive TFT formed on a substrate; an overcoat layer formed on the TFTs; a drain contact hole exposing portions of a drain electrode of the drive TFT by removing portions of the overcoat layer; a first electrode contacting to the drain electrode of the drive TFT; a bank pattern exposing an aperture area of a pixel; an organic layer formed on the first electrode; and a second electrode formed on the organic layer, wherein the bank pattern blocks regions where the drain contact hole is formed.
    Type: Grant
    Filed: August 9, 2010
    Date of Patent: April 10, 2012
    Assignee: LG Display Co., Ltd.
    Inventor: Heedong Choi
  • Patent number: 7858980
    Abstract: A phase change memory structure and method for forming the same, the method including providing a substrate comprising a conductive area; forming a spacer having a partially exposed sidewall region at an upper portion of the spacer defining a phase change memory element contact area; and, wherein the spacer bottom portion partially overlaps the conductive area. Both these two methods can reduce active area of a phase change memory element, therefore, reducing a required phase changing electrical current.
    Type: Grant
    Filed: March 1, 2004
    Date of Patent: December 28, 2010
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Shyue Lai, Chao-Hsiung Wang, Denny Tang, Wen-Chin Lin
  • Patent number: 7745315
    Abstract: A method for forming vertically oriented, crystallographically aligned nanowires (nanocolumns) using monolayer or submonolayer quantities of metal atoms to form uniformly sized metal islands that serve as catalysts for MOCVD growth of Group III nitride nanowires.
    Type: Grant
    Filed: October 3, 2007
    Date of Patent: June 29, 2010
    Assignee: Sandia Corporation
    Inventors: George T. Wang, Qiming Li, J. Randall Creighton
  • Patent number: 7732894
    Abstract: A method of mounting an electronic component on a substrate includes forming at least one trench in a surface of the substrate. The trenches formed in the substrate reduce a stiffness of the substrate, which provides less resistance to shear. Accordingly, the trenches reduce the amount of strain on the joints, which mount the electronic component to the substrate, which enhances the life of the joints.
    Type: Grant
    Filed: February 13, 2008
    Date of Patent: June 8, 2010
    Assignee: International Business Machines Corporation
    Inventors: David Questad, Vijayeshwar D. Khanna, Jennifer V. Muney, Arun Sharma, Sri M. Sri-Jayantha, Lorenzo Valdevit
  • Patent number: 7723771
    Abstract: A capacitor structure comprises a first and a second electrode of conducting material. Between the first and second electrodes, an atomic layer deposited dielectric film is disposed, which comprises zirconium oxide and a dopant oxide. Herein, the dopant comprises an ionic radius that differs by more than 24 pm from an ionic radius of zirconium, while the dielectric film comprises a dopant content of 10 atomic percent or less of the dielectric film material excluding oxygen. A process for fabricating a capacitor comprises a step of forming a bottom electrode of the capacitor. On the bottom electrode, a dielectric film comprising zirconium oxide is deposited, and a step for introducing a dopant oxide into the dielectric film performed. On the dielectric structure, a top electrode is formed.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: May 25, 2010
    Assignee: Qimonda AG
    Inventors: Tim Boescke, Uwe Schroeder
  • Patent number: 7723129
    Abstract: An electronic device (100) with one or more semiconductor chips (102) has an inductor (101) assembled on or under the chips. The inductor includes a ferromagnetic body (111) and a wire (104) wrapped around the body to form at least a portion of a loop; the wire ends (104a) are connected to the chips. The assembly is attached to a substrate (103), which may be a leadframe. The device may be encapsulated in molding compound (140) so that the inductor can double as a heat spreader (111c), enhancing the thermal device characteristics.
    Type: Grant
    Filed: April 3, 2009
    Date of Patent: May 25, 2010
    Assignee: Texas Instruments Incorporated
    Inventor: Sreenivasan K Koduri
  • Patent number: 7714440
    Abstract: Provided is a metal interconnection structure of a semiconductor device, including a first metal film pattern disposed on an upper part of an insulation film of a semiconductor substrate; an intermetallic dielectric film having a metal contact plug in which a barrier layer, a metal film for contact plug and a second metal film are sequentially disposed, on the first metal film pattern; and a second metal film pattern disposed on the metal contact plug and intermetallic dielectric film and connected to the metal contact plug.
    Type: Grant
    Filed: June 10, 2008
    Date of Patent: May 11, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: In Cheol Ryu, Sung-gon Jin
  • Patent number: 7714427
    Abstract: Integrate circuit die terminal arrangements and configurations for mounting an integrate circuit die on a package substrate to reduce package transmission paths. In one embodiment, terminals for signals sensitive to trace length outside a die are arranged at the corners of the die. The die is mounted on a package substrate in an angle with respect to a package substrate to point the corners of the die at the edges of the package substrate to reduce trace length outside the die. The center of the die may or may not coincide with the center of the substrate. In one embodiment, when compare to a centered, non-rotated die mounting position, mounting a die with corners pointing at the edges of the package substrate does not cause significant differences in substrate warpage.
    Type: Grant
    Filed: October 30, 2006
    Date of Patent: May 11, 2010
    Assignee: Intel Corporation
    Inventors: Chee Wai Wong, Chee Hoo Lee
  • Patent number: 7709309
    Abstract: It is an object of the present invention to control the plane orientation of crystal grains obtained by using a laser beam, into a direction that can be substantially regarded as one direction in an irradiation region of the laser beam. After forming a cap film over a semiconductor film, the semiconductor film is crystallized by using a CW laser or a pulse laser having a repetition rate of greater than or equal to 10 MHz. The obtained semiconductor film has a plurality of crystal grains having a width of greater than or equal to 0.01 ?m and a length of greater than or equal to 1 ?m. In a surface of the obtained semiconductor film, a ratio of an orientation {211} is greater than or equal to 0.4 within the range of an angle fluctuation of ±10°.
    Type: Grant
    Filed: October 12, 2006
    Date of Patent: May 4, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tomoaki Moriwaka
  • Patent number: 7709336
    Abstract: A semiconductor integrated circuit device. The device has a semiconductor substrate and a dielectric layer overlying the semiconductor substrate. The device also has a gate structure including edges. A metal hard mask layer is overlying the gate structure. A dielectric layer is formed sidewall spacers on the edges of the gate structure to protect the gate structure including the edges. An exposed portion of the metal hard mask layer is overlying the gate structure. A silicon germanium fill material is provided in an etched source region and an etched drain region. The etched source region and the etched drain region are each coupled to the gate structure. The device has a strained channel region between the filled source region and the filled drain region from at least the silicon germanium material formed in the etched source region and the etched drain region. An electrical connection is coupled to the metal hard mask overlying the gate structure.
    Type: Grant
    Filed: December 28, 2005
    Date of Patent: May 4, 2010
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Xian J. Ning, Hanming Wu, John Chen
  • Patent number: 7709333
    Abstract: A field effect transistor (FET) device includes a gate conductor formed over a semiconductor substrate, a source region having a source extension that overlaps and extends under the gate conductor, and a drain region having a drain extension that overlaps and extends under the gate conductor only at selected locations along the width of the gate conductor.
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: May 4, 2010
    Assignee: International Business Machines Corporation
    Inventors: Huilong Zhu, Oleg Gluschenkov
  • Patent number: 7709836
    Abstract: The invention relates to a detector arrangement (100), a method for the detection of electrical charge carriers and use of an ONO field effect transistor for detection of an electrical charge. The detector arrangement (100) has an ONO field effect transistor embodied on and/or in a substrate (101), for the detection of electrical charge carriers, such that the electrical charge carrier (103) for detection may be introduced into die ONO field effect transistor layer sequence (102), a recording unit (104), coupled to the ONO field effect transistor, for recording an electrical signal characteristic of the amount and/or the charge carrier type for the electrical charge carrier (103) introduced into the ONO layer sequence (102) and an analytical unit for determining the amount and/or the charge carrier type of the electrical charge carrier (103) introduced into the ONO layer sequence (102) from the characteristic electrical signal.
    Type: Grant
    Filed: March 12, 2003
    Date of Patent: May 4, 2010
    Assignee: Infineon Technologies AG
    Inventors: Bernhard Knott, Georg Tempel
  • Patent number: 7709850
    Abstract: A pixel structure and a fabrication method thereof are provided. The pixel comprises a substrate, a gate, a gate insulating layer, a channel layer, a first source/drain, a second source/drain, a dielectric layer, a first pixel electrode, and a second pixel electrode. The gate is disposed on the substrate and is covered by the gate insulating layer. The channel layer is disposed on the gate insulating layer above the gate. The first source/drain and the second source/drain are disposed on the channel layer. The channel layer has different thicknesses respectively corresponding to the first drain/source and the second drain/source. The dielectric layer covers the substrate and exposes the first and the second drains. The first and the second pixel electrodes are disposed on the dielectric layer, and are electrically connected to the first and the second drains respectively.
    Type: Grant
    Filed: November 8, 2006
    Date of Patent: May 4, 2010
    Assignee: Au Optronics Corporation
    Inventor: Ching-Yi Wang
  • Patent number: 7704825
    Abstract: A memory capable of reducing the memory cell size is provided. This memory includes a first conductive type first impurity region formed on a memory cell array region of the main surface of a semiconductor substrate for functioning as a first electrode of a diode included in a memory cell and a plurality of second conductive type second impurity regions, formed on the surface of the first impurity region at a prescribed interval, each functioning as a second electrode of the diode.
    Type: Grant
    Filed: April 28, 2008
    Date of Patent: April 27, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Kouichi Yamada
  • Patent number: 7700451
    Abstract: Embodiments relate to a method of manufacturing a transistor having a metal silicide layer. In embodiments, the method may include sequentially forming a gate insulating layer pattern and a gate conductive layer pattern on a semiconductor substrate, forming a first metal silicide layer on the gate conductive layer pattern and a second metal silicide layer on the semiconductor substrate, forming a spacer layer on side-walls of the gate insulating layer pattern and the gate conductive layer pattern, and forming a source/drain region in the semiconductor substrate below the second metal silicide layer by performing ion implantation.
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: April 20, 2010
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Pyoung On Cho
  • Patent number: 7700464
    Abstract: Methods and devices are provided for transforming non-planar or planar precursor materials in an appropriate vehicle under the appropriate conditions to create dispersions of planar particles with stoichiometric ratios of elements equal to that of the feedstock or precursor materials, even after selective forces settling. In particular, planar particles disperse more easily, form much denser coatings (or form coatings with more interparticle contact area), and anneal into fused, dense films at a lower temperature and/or time than their counterparts made from spherical nanoparticles. These planar particles may be nanoflakes that have a high aspect ratio. The resulting dense films formed from nanoflakes are particularly useful in forming photovoltaic devices.
    Type: Grant
    Filed: February 23, 2006
    Date of Patent: April 20, 2010
    Assignee: Nanosolar, Inc.
    Inventors: Matthew R. Robinson, Jeroen K. J. Van Duren, Craig Leidholm, Brian M. Sager
  • Patent number: 7696036
    Abstract: An NFET containing a first high-k dielectric portion and a PFET containing a second high-k gate dielectric portion are formed on a semiconductor substrate. A gate sidewall nitride is formed on the gate of the NFET, while the sidewalls of the PFET remain free of the gate sidewall nitride. An oxide spacer is formed directly on the sidewalls of a PFET gate stack and on the gate sidewall nitride on the NFET. After high temperature processing, the first and second dielectric portions contain a non-stoichiometric oxygen deficient high-k dielectric material. The semiconductor structure is subjected to an anneal in an oxygen environment, during which oxygen diffuses through the oxide spacer into the second high-k dielectric portion. The PFET comprises a more stoichiometric high-k dielectric material and the NFET comprises a less stoichiometric high-k dielectric material. Threshold voltages of the PFET and the NFET are optimized by the present invention.
    Type: Grant
    Filed: June 14, 2007
    Date of Patent: April 13, 2010
    Assignee: International Business Machines Corporation
    Inventors: Huiming Bu, Eduard A. Cartier, Bruce B. Doris, Young-Hee Kim, Barry Linder, Vijay Narayanan, Vamsi K. Paruchuri, Michelle L. Steen
  • Patent number: 7695982
    Abstract: A wafer comprising a low-k dielectric layer is refurbished for reuse. Initially, a removable layer is provided on the wafer. The low-k dielectric layer is formed over the removable layer. The overlying low-k dielectric layer is removed from the wafer by etching away the removable layer by at least partially immersing the wafer in an etching solution. Thereafter, another low-k dielectric layer can be formed over another removable layer.
    Type: Grant
    Filed: April 19, 2007
    Date of Patent: April 13, 2010
    Assignee: Applied Matreials, Inc.
    Inventors: Hong Wang, Krishna Vepa, Paul V. Miller
  • Patent number: 7696026
    Abstract: An array substrate for a liquid crystal display device includes a substrate, a plurality of thin film transistors formed on the substrate, each thin film transistor includes a gate electrode, a first gate insulation layer, a second gate insulation layer, an active layer, an ohmic contact layer, a source electrode and a drain electrode, a plurality of gate lines, a plurality of data lines disposed orthogonal to the plurality of gate lines, a plurality of pixel electrodes disposed at pixel regions defined by intersections of the plurality of gate lines and the plurality of data lines, each pixel electrode electrically contacting each drain electrode of the plurality of thin film transistors, and a plurality of storage capacitors each including a portion of each gate line as a first capacitor electrode, the first gate insulation layer as a dielectric layer, and a capacitor electrode electrically communicating with each pixel electrode and functioning as a second capacitor electrode with a portion of each pixel e
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: April 13, 2010
    Assignee: LG Display Co., Ltd.
    Inventor: Kyo-Ho Moon