Patents Examined by M. Wilczewski
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Patent number: 7696036Abstract: An NFET containing a first high-k dielectric portion and a PFET containing a second high-k gate dielectric portion are formed on a semiconductor substrate. A gate sidewall nitride is formed on the gate of the NFET, while the sidewalls of the PFET remain free of the gate sidewall nitride. An oxide spacer is formed directly on the sidewalls of a PFET gate stack and on the gate sidewall nitride on the NFET. After high temperature processing, the first and second dielectric portions contain a non-stoichiometric oxygen deficient high-k dielectric material. The semiconductor structure is subjected to an anneal in an oxygen environment, during which oxygen diffuses through the oxide spacer into the second high-k dielectric portion. The PFET comprises a more stoichiometric high-k dielectric material and the NFET comprises a less stoichiometric high-k dielectric material. Threshold voltages of the PFET and the NFET are optimized by the present invention.Type: GrantFiled: June 14, 2007Date of Patent: April 13, 2010Assignee: International Business Machines CorporationInventors: Huiming Bu, Eduard A. Cartier, Bruce B. Doris, Young-Hee Kim, Barry Linder, Vijay Narayanan, Vamsi K. Paruchuri, Michelle L. Steen
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Patent number: 7691757Abstract: Methods are provided for pulsed chemical vapor deposition (CVD) of complex nitrides, such as ternary metal nitrides. Pulses of metal halide precursors are separated from one another and nitrogen-containing precursor is provided during the metal halide precursor pulses as well as between the metal halide precursor pulses. Two different metal halide precursors can be provided in simultaneous pulses, alternatingly, or in a variety of sequences. The nitrogen-containing precursor, such as ammonia, can be provided in pulses simultaneously with the metal halide precursors and between the metal halide precursors, or continuously throughout the deposition. Temperatures can be kept between about 300° C. and about 700° C.Type: GrantFiled: June 21, 2007Date of Patent: April 6, 2010Assignee: ASM International N.V.Inventors: Suvi P. Haukka, Tanja Claasen, Peter Zagwijn
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Patent number: 7691699Abstract: Disclosed herein is a transistor for a semiconductor device and a method of forming the same. According to the present invention, a recess channel region is formed on a cell region to increase a channel length and a fin-type channel region is simultaneously formed on a peripheral circuit region to increase a channel area so as to simplify process steps, thereby improving the yield and productivity for manufacturing a semiconductor device.Type: GrantFiled: December 30, 2005Date of Patent: April 6, 2010Assignee: Hynix Semiconductor Inc.Inventors: Sung Woong Chung, Sang Don Lee
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Patent number: 7691678Abstract: A solid-state imaging device comprises a housing in which a base and ribs forming a rectangular frame are formed in one piece by a resin; a plurality of metal lead pieces embedded in the housing, each of which has an internal terminal portion facing an internal space of the housing and an external terminal portion exposed at an outer portion of the housing; an imaging element arranged on the base in the internal space of the housing; connecting members connecting electrodes of the imaging element to the internal terminal portions of the metal lead pieces; and a transparent plate fastened to an upper face of the ribs. The upper face of the ribs is provided with a lower step portion that is lowered along an external periphery, and the transparent plate is fastened to the upper face of the ribs by an adhesive filled at least into the lower step portion.Type: GrantFiled: April 3, 2008Date of Patent: April 6, 2010Assignee: Panasonic CorporationInventors: Katsutoshi Shimizu, Masanori Minamio, Kouichi Yamauchi
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Patent number: 7687329Abstract: One aspect of this disclosure relates to a method for creating proximity gettering sites in a silicon on insulator (SOI) wafer. In various embodiments of this method, a relaxed silicon germanium region is formed over an insulator region of the SOI to be proximate to a device region. The relaxed silicon germanium region generates defects to getter impurities from the device region. Other aspects are provided herein.Type: GrantFiled: July 27, 2006Date of Patent: March 30, 2010Assignee: Micron Technology, Inc.Inventor: Leonard Forbes
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Patent number: 7687378Abstract: A fabricating method of nitride semiconductor substrate is provided. First, a first substrate including a first base material, a nitride semiconductor template layer stacked on the first base material, and a first dielectric layer stacked on the nitride semiconductor template layer is provided. Then, the first dielectric layer and the nitride semiconductor template layer are patterned, and a second substrate including a second base material and a second dielectric layer stacked on the second base material is provided. Next, the nitride semiconductor template layer and the first dielectric layer of the first substrate are transferred onto the second dielectric layer of the second substrate through bonding and transferring processes, and then a nitride semiconductor thick film is grown from the nitride semiconductor template layer through an epitaxy process. After that, the nitride semiconductor thick film and the second substrate are separated.Type: GrantFiled: August 25, 2006Date of Patent: March 30, 2010Assignee: Industrial Technology Research InstituteInventors: Po-Chun Liu, Wen-Yueh Liu, Chih-Ming Lai, Yih-Der Guo, Jenq-Dar Tsay
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Patent number: 7687380Abstract: In order to promote an effect of laser annealing in respect of a semiconductor film, moisture is intentionally included in an atmosphere in irradiating laser beam to these miconductor film by which a temperature holding layer comprising water vapor is formed on the surface of these miconductor film in irradiating the laser beam and the laser annealing operation can be performed effectively.Type: GrantFiled: March 26, 2008Date of Patent: March 30, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Naoto Kusumoto, Shunpei Yamazaki, Koichiro Tanaka
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Patent number: 7682880Abstract: Primitive cells, which are circuit patterns of the constituent elements of a semiconductor device, are arranged in the element formation area of a semiconductor device, and at least one fill cell with a diffusion layer and no wiring, is arranged in the vacant areas that are generated in the element formation area after the primitive cells have been arranged.Type: GrantFiled: March 14, 2007Date of Patent: March 23, 2010Assignee: NEC Electronics CorporationInventors: Hidekazu Kawashima, Tetsuya Katoh
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Source/drain electrodes, transistor substrates and manufacture methods, thereof, and display devices
Patent number: 7683370Abstract: In a thin-film transistor substrate including a substrate, a thin-film transistor semiconductor layer, a source/drain electrode, and a transparent pixel electrode, the source/drain electrode includes a thin film of an aluminum alloy containing 0.1 to 6 atomic percent of nickel as an alloy element, and the aluminum alloy thin film is directly connected to the thin-film transistor semiconductor layer.Type: GrantFiled: August 2, 2006Date of Patent: March 23, 2010Assignee: Kobe Steel, Ltd.Inventors: Toshihiro Kugimiya, Hiroshi Gotoh -
Patent number: 7679130Abstract: Deep trench isolation structures and methods of formation thereof are disclosed. Several methods of and structures for increasing the threshold voltage of a parasitic transistor formed proximate deep trench isolation structures are described, including implanting a channel stop region into the bottom surface of the deep trench isolation structures, partially filling a bottom portion of the deep trench isolation structures with an insulating material, and/or filling at least a portion of the deep trench isolation structures with a doped polysilicon material.Type: GrantFiled: March 3, 2006Date of Patent: March 16, 2010Assignee: Infineon Technologies AGInventors: Armin Tilke, Danny Pak-Chum Shum, Laura Pescini, Ronald Kakoschke, Karl Robert Strenz, Martin Stiftinger
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Patent number: 7678592Abstract: In an LED housing, a heat conducting part has a chip mounting area, a heat connecting area opposed to the chip mounting area and a groove formed adjacent to the heat connecting area. An electrical connecting part has a wiring area placed adjacent to the chip mounting area and an external power connecting area led to the wiring area. A housing body is made of molding resin, and integrally holds the heat conducting part and the electrical connecting part while isolating the electrical connecting part from the heat conducting part. The housing body is provided with a recess extended from a portion of the groove of the heat conducting part to a side of the housing body.Type: GrantFiled: March 1, 2007Date of Patent: March 16, 2010Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Seon Goo Lee, Bum Joon Jin, Kyung Taeg Han, Chang Wook Kim
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Patent number: 7678589Abstract: A method for manufacturing a capacitive semiconductor sensor includes: forming a plurality of circuit chips in a wafer, wherein each circuit chip includes a pad for testing a sensor chip; bonding the sensor chip on each circuit chip with a bump so that the sensor chip is electrically coupled with the circuit chip, wherein each sensor chip is made of semiconductor and has a capacitance changing portion, which is disposed on one side of the sensor chip and has a variable capacitance, wherein the circuit chip detects a capacitance change of the sensor chip, and wherein the one side of the sensor chip faces the circuit chip; testing each sensor chip through the pad; and cutting the wafer into individual circuit chips so that the circuit chip and the sensor chip provide the capacitive semiconductor sensor.Type: GrantFiled: March 20, 2007Date of Patent: March 16, 2010Assignee: DENSO CORPORATIONInventors: Minekazu Sakai, Tameharu Oota
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Patent number: 7675145Abstract: The present embodiments provide surface mount devices and/or systems. In some embodiments, the surface mount devices comprise a casing with a recess in a second surface; a first lead element partially encased by the casing comprising a coupling portion extending interior to the casing generally in a first direction and a chipset portion extending from the first coupling portion at a first acute angle and through an area exposed by the recess; a second lead element partially encased by the casing comprising a second coupling portion extending interior to the casing in a second direction substantially parallel to the first direction and a head portion extending from the second coupling portion at a second acute angle and partially terminating interior to the area exposed by the recess; and the chipset portion comprises a first indentation and a second indentation both extending into the area exposed through the recess.Type: GrantFiled: March 28, 2006Date of Patent: March 9, 2010Assignee: Cree Hong Kong LimitedInventors: Xuan Wong, Jian Hui Xie, Siu Cheong Cheng
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Patent number: 7670862Abstract: A method of manufacturing a silicon optoelectronic device, a silicon optoelectronic device manufactured by the method, and an image input and/or output apparatus having the silicon optoelectronic device are provided. The method includes: preparing an n-type or p-type silicon-based substrate; forming a polysilicon in one or more regions of the surface of the substrate; oxidizing the surface of the substrate where the polysilicon is formed, to form a silicon oxidation layer on the substrate, and forming a microdefect flection pattern at the interface between the substrate and the silicon oxidation layer, wherein the microdefect flection pattern is formed by the oxidation accelerated by oxygen traveling through boundaries of the grains in the polysilicon; exposing the microdefect flection pattern by etching the silicon oxidation layer; and forming a doping region by doping the exposed microdefect flection pattern with a dopant of the opposite type to the substrate.Type: GrantFiled: November 22, 2005Date of Patent: March 2, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: In-jae Song, Byoung-Iyong Choi
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Patent number: 7671385Abstract: An image sensor contains a semiconductor substrate, a plurality of pixels defined on the semiconductor substrate, a photo conductive layer and a transparent conductive layer formed on the pixel electrodes of the pixels in order, and a shield device positioned between any two adjacent pixel electrodes. The shield device has a shield electrode and an isolation structure surrounding the shield electrode so that the shield electrode is isolated from the pixel electrodes and the photo conductive layer by the isolation structure.Type: GrantFiled: March 15, 2007Date of Patent: March 2, 2010Assignee: Powerchip Semiconductor Corp.Inventors: Hsin-Heng Wang, Chiu-Tsung Huang, Shih-Siang Lin
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Patent number: 7670944Abstract: Method and structures are provided for conformal lining of dual damascene structures in integrated circuits. Trenches and contact vias are formed in insulating layers. The trenches and vias are exposed to alternating chemistries to form monolayers of a desired lining material. Exemplary process flows include alternately pulsed metal halide and ammonia gases injected into a constant carrier flow. Self-terminated metal layers are thus reacted with nitrogen. Near perfect step coverage allows minimal thickness for a diffusion barrier function, thereby maximizing the volume of a subsequent filling metal for any given trench and via dimensions.Type: GrantFiled: August 28, 2006Date of Patent: March 2, 2010Assignee: ASM International N.V.Inventors: Ivo Raaijmakers, Suvi P. Haukka, Ville A. Saanila, Pekka J. Soininen, Kai-Erik Elers, Ernst H.A. Granneman
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Patent number: 7671405Abstract: A method of forming at least a portion of a dual bit memory core array upon a semiconductor substrate, the method comprising performing front end processing, performing a first bitline implant, or pocket implants, or both into the first bitline spacings to establish buried first bitlines within the substrate, depositing a layer of the spacer material over the charge trapping dielectric and the polysilicon layer features, forming a sidewall spacer adjacent to the charge trapping dielectric and the polysilicon layer features to define second bitline spacings between adjacent memory cells, performing a deep arsenic implant into the second bitline spacings to establish a second bitline within the structure that is deeper than the first bit line, removing the sidewall spacers and performing back end processing.Type: GrantFiled: December 26, 2006Date of Patent: March 2, 2010Assignee: Spansion LLCInventors: Timothy Thurgate, Yi He, Ming-Sang Kwan, Zhizheng Liu, Xuguang Wang
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Patent number: 7670859Abstract: A method for manufacturing a semiconductor device, includes: preparing a semiconductor module including: a semiconductor substrate having an electrode; a test pad electrically connected to the electrode; a land electrically connected to the test pad; and an external terminal provided on the land; and testing an electrical characteristic by bringing a probe into contact with the test pad.Type: GrantFiled: October 20, 2006Date of Patent: March 2, 2010Assignee: Seiko Epson CorporationInventor: Terunao Hanaoka
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Patent number: 7670933Abstract: A method for growing high quality, nonpolar Group III nitrides using lateral growth from Group III nitride nanowires. The method of nanowire-templated lateral epitaxial growth (NTLEG) employs crystallographically aligned, substantially vertical Group III nitride nanowire arrays grown by metal-catalyzed metal-organic chemical vapor deposition (MOCVD) as templates for the lateral growth and coalescence of virtually crack-free Group III nitride films. This method requires no patterning or separate nitride growth step.Type: GrantFiled: October 3, 2007Date of Patent: March 2, 2010Assignee: Sandia CorporationInventors: George T. Wang, Qiming Li, J. Randall Creighton
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Patent number: 7670867Abstract: The method for manufacturing a CMOS image sensor is employed to prevent bridge phenomenon between adjacent microlenses by employing openings between the microlenses. The method includes the steps of: preparing a semiconductor substrate including isolation regions and photodiodes therein obtained by a predetermined process; forming an interlayer dielectric (ILD), metal interconnections and a passivation layer formed on the semiconductor substrate in sequence; forming a color filter array having a plurality of color filters on the passivation layer; forming an over-coating layer (OCL) on the color filter array by using a positive photoresist or a negative photoresist; forming openings in the OCL by patterning the OCL by using a predetermined mask; and forming dome-typed microlenses on a patterned OCL.Type: GrantFiled: October 3, 2005Date of Patent: March 2, 2010Inventors: Chang-Young Jeong, Dae-Ung Shin, Hong-Ik Kim