Abstract: Embodiments of the present invention provide a split vertex buffer where the data for each vertex is split between parallel vertex buffers. The first buffer contains vertex X and Y data, while the second parallel buffer contains the remainder of the vertex data. Given the split vertex buffers, the hardware binning-engine is now permitted to read and cache only vertex screen X and Y data. Especially given a typically high level of temporal coherency between indexed vertex references, the reading and caching of large parcels of vertex screen-space X and Y leads to lower and highly efficient utilization of memory bandwidth for hardware binning input. Embodiments of the present invention thus reduce the hardware binning memory bandwidth requirements and improve memory utilization.

Abstract: In general, and in a form of the present invention, a method is provided for reducing execution time of a program executed on a digital system by improving hit rate in a cache of the digital system. This is done by determining cache performance during execution of the program over a period of time as a function of address locality, and then identifying occurrences of cache conflict between two program modules. One of the conflicting program modules is then relocated so that cache conflict is eliminated or at least reduced. In one embodiment of the invention, a 2D plot of cache operation is provided as a function of address versus time for the period of time. A set of cache misses having temporal locality and spatial locality is identified as a horizontally arranged grouping of pixels at a certain address locality having a selected color indicative of a cache miss.

Abstract: A gaze directed visual system includes a gaze tracker for determining an area of interest; an image generator for generating an area of interest image about the area of interest and generating a background image elsewhere; paired field buffers, for each field of view, for providing a composite image from the area of interest image and the background image; and a timing and control block for interleaving timing of read and write operations on each pair of field buffers whereby reading of the composite image commences upon completion of writing a first portion of the background image so that transport delay is minimized in displaying the composite image on a high resolution display device.

Abstract: A cache for a graphics system storing both an address tag and an identification number for each block of data stored in the data cache. An address and identification number of a requested block of data is provided to the cache, and is checked against all of the address and identification number entries present. A block of data is provided if both the address and the identification number of the requested data matches an entry in the cache. However, if the address of the requested data is not present, or if the address matches an entry but the associated identification number does not match, a cache miss occurs, and the requested graphics data must be retrieved from a system memory. The address and identification number are updated, and the requested data replaces the former graphics data in the data cache. As a result, a block of data stored in the cache having the same address as the requested data, but having data that is invalid, can be invalidated without invalidating the entire cache.

Abstract: Methods and apparatus for use with AGP-capable computer systems are disclosed. Since each AGP-capable chipset can have a unique range of graphics port aperture sizes that it supports, current graphics port aperture drivers are chipset-specific, with hard-coded tables of supported graphics aperture sizes. Described herein is a driver that dynamically ascertains the range of supported graphics aperture port sizes for an attached AGP-capable chipset, thus allowing this driver to be ported between different chipsets without manual reconfiguration and recompiling. The method employed in the driver sends one or more test aperture size values to a register resident in the chipset, and then reads what is written to see if the chipset changed any of the bits of the test value. The method infers supported sizes from examining which, if any bits, were changed by the chipset.

Abstract: In a display apparatus, a display instruction generating unit outputs a display instruction. A plurality of display processing units are arranged in parallel, and each of the plurality of display processing units generates display data in response to the display instruction from the display instruction generating unit. A display switching unit selects one of the plurality of display processing units and outputs the display data from the selected display processing unit to the display unit. Thus, a display unit displays the display data.

Abstract: The data transfer device for transferring data between a system bus and a local memory having a frame buffer region and a general region includes an interface section and a data processor. The interface section generates a transfer parameter for accessing one of the frame buffer region and the general region based on control data for controlling data transfer sent from the system bus and outputs the generated transfer parameter, in addition to transferring data to/from the system bus. The data processor generates an address of data to be transferred in the local memory according to the transfer parameter, and transfers data to/from the local memory using the generated address, in addition to transferring data to/from the interface section.

Abstract: A method of storing a texel in a texel cache comprising reading a t coordinate of the texel, the t coordinate comprising a plurality of bits, reading a s coordinate of the texel, the s coordinate comprising a plurality of bits, forming an offset by concatenating bits of the t coordinate with bits of the s coordinate and forming an index by concatenating bits of the t coordinate with bits of the s coordinate is discussed.

Abstract: A texture data reading apparatus includes a cache memory including a plurality of read ports and a plurality of regions to store pixel texture data. An address comparator includes a plurality of input ports to receive incoming pixels, wherein the address comparator compares the memory addresses associated with the incoming pixels to determine which regions of cache memory are accessed. A cache lookup device accesses new texture data from the cache memory for the incoming pixels in the same clock cycle in response to the number of memory regions accessed being less than or equal to the number of cache memory read ports.

Abstract: Disclosed are methods and systems for interfaces between video applications and display screens that allow applications to intelligently use display resources of their host device without tying themselves too closely to operational particulars of that host. Video applications (1) receive information about the display environment from a graphics arbiter, (2) use that information to prepare their video output, and (3) send their output to the graphics arbiter which efficiently presents that output to the display screen. The graphics arbiter tells applications the estimated time when the next frame will be displayed on the screen. Applications tailor their output to the estimated display time, thus improving output quality while decreasing resource waste by avoiding the production of “extra” frames. The graphics arbiter tells an application when its output is fully or partially occluded so that the application need not expend resources to draw portions of frames that are not visible.

Abstract: A system is described that is broadly directed to a system of integrated circuit components. The system comprises a plurality of nodes that are interconnected by communication links. A random access memory (RAM) is connected to each node. At least one functional unit is integrated into each node, and each functional unit is configured to carry out a predetermined processing function. Finally, each RAM includes a coherency mechanism configured to permit only read access to the RAM by other nodes, the coherency mechanism further configured to permit write access to the RAM only by functional units that are local to the node.

Abstract: An uninterrupted data display method for a computer system having a system memory directly accessed by a processor, for preventing disrupted data display from transmission break is disclosed. The method is accomplished before the processor goes into a non-responding period due to an execution of an economical process. The method includes the steps of: (i) providing a data storage device having a depth for storing a period long of data. (ii) Comparing the period of said depth to the non-responding period, if the period of said depth is longer than the non-responding period, jump to step (iii), otherwise, to step (iv). (iii) Loading the period long of data from a system memory into the data storage device then jump to step (v). (iv) Detecting a synchronization pulse then jump to step (v), wherein step (v) is to be accomplished within a non-display period, and, (v) executing the economical process.

Abstract: An image data processing method and system receives image data from a burst memory buffer and provides output image data to a vertical filter for filtering. The method determines whether a new frame of input image data has been received, said frame of data having a plurality of blocks, each block having a plurality of rows and columns. A vertical input buffer uses a read pointer, an oldest unused data pointer, and a write pointer to keep track of the data that is being read and stored. Data is read and stored into said vertical input buffer by determining the minimum offset for the block, reading a row of input image data from the burst memory buffer and skipping the row depending on the minimum offset until minimum offset reached, and storing the row of input image data in said vertical input buffer for processing by the vertical filter until the buffer is full. If the entire frame has been processed then the pointers are all reset.

Abstract: An image process unit includes an image input interface that receives inputs of image data from a scanner and generates data packets, an image ring interface 4 that transfer the data packets to an image ring interface 2, and an image output interface that outputs image data to a printer, and a system control unit includes a RAM controller that has a RAM store the data packets transferred from the image process unit and reads the data packets from the RAM, and an image ring interface 1 that transfers the data packets to an image ring interface 3, where packet transfers from the image process unit to the system control unit and in its reverse direction are conducted using mutually different image rings.

Abstract: An image processing integrated circuit including a CPU configured to supply an image data, frame information of the image data and a first write destination address indicating an address to which the image data is written; a latch circuit configured to receive the frame information from the CPU; an address scrambler configured to allocate second write destination addresses based on the first write destination address supplied from the CPU and the frame information supplied from the latch circuit; a RAM configured to store the image data supplied from the CPU according to the second write destination address supplied from the address scrambler; and a DA converter configured to perform the digital-analog conversion for the image data supplied from the RAM and for supplying a first read destination address corresponding to the first write destination address one to one, to the address scrambler after the conversion.

Abstract: A multimedia data decoding apparatus to decode multimedia data and method thereof includes a data information extracting unit extracting detail information from the multimedia data. An input buffering unit stores the multimedia data for a predetermined time. A decoding unit decodes the multimedia data from the input buffering unit into original signals of respective types. An output buffering unit stores the decoded multimedia data for a predetermined time. A control unit determines buffering capacities of the input buffering unit and the output buffering unit based on the detail information extracted by the data information extracting unit.

Abstract: A system and method for managing memory in display processing circuit for use with a color sequential display. The system comprises: a shared memory; and a storage queue coupled to the shared memory, wherein the storage queue includes: a system for receiving and storing alternating packets of color-specific video data in the storage queue; and a system for separately reading contiguous sets color-specific packets from the storage queue to the shared memory.

Abstract: A system, method, and computer program product for creating a sequence of computer graphics frames, using a plurality of rendering pipelines. For each frame, each rendering pipeline receives a subset of the total amount of graphics data for the particular frame. At the completion of a frame, each rendering pipeline sends a performance report to a performance monitor. The performance monitor determines whether or not there was a significant disparity in the time required by the respective rendering pipelines to render their tiles. If a disparity is detected, and if the disparity is determined to be greater than some threshold, an allocation module resizes the tiles for the next frame. This serves to balance the load across rendering pipelines for each frame.

Abstract: According to one embodiment, a computer system is disclosed. The computer system includes a graphics accelerator and a graphics cache coupled to the graphics accelerator. The graphics cache stores texture data, color data and depth data.

Abstract: In one embodiment, a computer system includes a first component configured to output data on a bus in response to a request for data from a second component. The data output by the first component may include both the requested data and unrequested data, and the unrequested data may have an unpredictable value. A controller coupled to the bus may be configured to replace the unrequested data with data that has a predictable value. A signature analysis register included in the second component is configured to capture the requested data and the predictable data output by the controller. Thus, the signature captured in the second component may be predictable, despite the unpredictable data output by the first component.