Abstract: The pseudo-linear frame buffer mapping system and method facilitates the clearing of the frame buffer memory of a graphics display system by subdividing the region of the frame buffer which is to be cleared into a plurality of sub-regions and by initiating the clear command concurrently to each of the plurality of sub-regions.

Abstract: A memory controller hub includes a graphics subsystem adapted to perform graphics operations on data and a cache adapted to store of locations in physical memory available to the graphics subsystem for storing graphics data and available to a graphics controller coupled to the memory controller hub to store graphics data.

Abstract: A graphical display system utilizes a plurality of graphics pipelines, a compositor, and application interface logic. The plurality of graphics pipelines are configured to render graphical data in parallel. The compositor is configured to define a composite data signal that is based on the graphical data rendered by each of the pipelines. The application interface logic is configured to retrieve configuration data indicative of a configuration of the compositor. The application interface logic is further configured to provide the configuration data to a graphics application, wherein the graphics application is configured to provide graphical data to the plurality of pipelines based on the configuration data.

Abstract: Methods and apparatus for implementing a pixel page system providing swapped pixel pages for use with a GLV (grating light valve).

Abstract: A method and apparatus for hardware rotation is described. In one embodiment, the invention is an apparatus. The apparatus includes a direct access address translation component. The apparatus also includes a frame buffer coupled to the direct access address translation component. The apparatus further includes a 2D coordinate translation component. The apparatus also includes a 2D engine coupled to the 2D coordinate translation component and to the frame buffer. The apparatus further includes a 3D engine. The apparatus also include a 3D coordinate translation component coupled to the 3D engine and the frame buffer. As will be appreciated, further embodiments of the invention are within the spirit and scope of the claimed invention, and the specific details of a specific embodiment as described need not be present in all embodiments of the invention.

Abstract: A media processing system is provided including a DRAM that includes a plurality of storage locations for storing digital data being processed by said media processing system, said digital data including video data that is compressed in a standardized format, a system for processing said digital data that includes said standardized format compressed video data to produce compressed video images and image data, a system for decoding said standardized format compressed video images to generate full motion video pixel data, a system for sharing said DRAM between said processing means and said decoding means, and a system for producing a full motion video signal from said full motion video pixel data. The media processing system may also have a system for multiplying or combining a first pixel by a second pixel in a single clock cycle.

Abstract: A drawing apparatus of the present invention includes: a display element on which images are displayed; and a plurality of loosely coupled drawing elements each of which executes drawing processing in parallel. At an update time predetermined for a display screen of the display element, each of the drawing elements updates the display screen only if none of the drawing elements is executing drawing processing. A parallel drawing method of the present invention executed by a plurality of drawing elements, each of which executes drawing processing, includes: receiving a drawing instruction; and updating the display screen of the display element by each of the drawing elements only if none of the drawing elements is executing drawing processing at an update time predetermined for the display screen.

Abstract: Usage semantics allow for shaders to be authored independently of the actual vertex data and accordingly enables their reuse. Usage semantics define a feature that binds data between distinct components to allow them to work together. In various embodiments, the components include high level language variables that are bound by an application or by vertex data streams, high level language fragments to enable several fragments to be developed separately and compiled at a later time together to form a single shader, assembly language variables that get bound to vertex data streams, and parameters between vertex and pixel shaders. This allows developers to be able to program the shaders in the assembly and high level language with variables that refer to names rather than registers. By allowing this decoupling of registers from the language, developers can work on the language separately from the vertex data and modify and enhance high level language shaders without having to manually manipulate the registers.

Abstract: The present invention is for easily drawing a polygon model having borderlines at high-speed. The video game machine comprises a recording medium 200 for enlarging the 3-D model where a normal vector of each polygon faces the outside at a predetermined enlargement ratio, overlaying a back model, where a normal vector of each polygon faces the inside, onto the above model and storing the integrated model as a framed model in advance, and a drawing processor 10 for drawing only polygons facing the direction of the view point position of the virtual camera in a virtual game space on the monitor 22 based on the drawing instructions of the framed model.

Abstract: An improved raster engine adapted to render video data from a frame buffer to one of a plurality of disparate displays is disclosed which comprises an integral bounded video signature analyzer, a hardware cursor apparatus supporting dual scanned displays, programmatic support for multiple disparate display types, multi-mode programmable hardware blinking, programmable multiple color depth digital display interface, and programmable matrix controlled grayscale generation.

Abstract: A system and method for synchronizing image display and buffer swapping in a multiple processor-multiple display environment. In a master-slave dichotomy, one processor or system is deemed the master and the others act as slaves. The master generates signals used to control vertical retrace and buffer swapping for itself and the slaves. In addition, a synchronization signal generator is provided to synchronize a timing signal between the master and slave systems.

Abstract: Methods and apparatus for storing data using two-dimensional arrays mapped to memory locations.

Abstract: Methods and apparatus for adjusting the geometry of buffer pages.

Abstract: A method for processing 2D operations in a tiled graphics architecture is disclosed. A graphics controller processes both 3D primitives and 2D blit operations. The 3D primitives are sorted into bins using well-known techniques. When a 2D blit operation is to be processed, the 2D blit operation is also sorted into bins. The sorted 3D primitives and sorted 2D blit operations are then delivered to blit and rendering engines on a bin-by-bin basis. By sorting the 2D blit operations into bins along with the 3D primitives, there is no need to flush the bins (send primitives to rendering engines) whenever a 2D blit operation requires processing. The sorting of 2D blit operations into bins reduces the frequency of graphics cache misses and improves graphics memory bandwidth utilization, thereby improving overall computer system performance.

Abstract: A memory chip having fast access to pixel data of graphics image to be stored therein is described. The memory chip consists of data inputs and outputs (I/Os) divided into a plurality of blocks; memory arrays for storing data received from or sent to the I/Os, which are divided into the same number of blocks as the I/Os; and address input terminals for specifying addresses to be accessed by respective blocks of the memory arrays, which are divided into the same number of blocks as the memory arrays. The memory chip and the method for storing data enable reading data in a vertical line, in a diagonal line, and the like, at the same access speed as data in a horizontal line is being read. Furthermore, power consumption of the chip is significantly reduced, and the wiring arrangement of the I/Os is greatly simplified.

Abstract: A graphics system and method for storing pixel values into or reading pixel values from a sample buffer, wherein the sample buffer is configured to store a plurality of samples for each of a plurality of pixels. The graphics system comprises a sample buffer, a programmable register, and a graphics processor. The programmable register stores a value indicating a method for pixel to sample conversion, and is preferably software programmable (e.g., user programmable). The graphics processor accesses the memory to determine a method for pixel to sample conversion and stores the pixel values in the sample buffer according to the determined method. A first method for pixel to sample conversion may specify a pixel write to all of the pixel's supporting samples. A second method for pixel to sample conversion may specify a pixel write to a selected one of the pixel's supporting samples.

Abstract: A system and method for synchronizing image display and buffer swapping in a multiple processor-multiple display environment. In a master-slave dichotomy, one processor or system is deemed the master and the others act as slaves. The master generates signals used to control vertical retrace and buffer swapping for itself and the slaves. In addition, a synchronization signal generator is provided to synchronize a timing signal between the master and slave systems.

Abstract: The image formation apparatus comprises a plurality of hard disk drives which store image data and a hard disk drive array control integrated circuit which controls reading/writing of image data from/into the hard disk drives. The hard disk drive array control integrated circuit executes setting of parameters, issuance of commands, and reading of statuses for all the hard disk drives substantially at the same time, divides the image data into pieces, and executes direct memory access transfer of the pieces of the image data to the hard disk drives substantially at the same time.

Abstract: A method and computer graphics system capable of implementing multiple pipelines for the parallel processing of graphics data. For certain data, a requirement may exist that the data be processed in order. The graphics system may use a set of tokens to reliably switch between ordered and unordered data modes. Furthermore, the graphics system may be capable of super-sampling and performing real-time convolution. In one embodiment, the computer graphics system may comprise a graphics processor, a sample buffer, and a sample-to-pixel calculation unit. The graphics processor may be configured to receive graphics data and to generate a plurality of samples for each of a plurality of frames. The sample buffer, which is coupled to the graphics processor, may be configured to store the samples. The sample-to-pixel calculation unit is programmable to generate a plurality of output pixels by filtering the rendered samples using a filter.

Abstract: An efficient graphics pipeline with a pixel cache and data pre-fetching. By combining the use of a pixel cache in the graphics pipeline and the pre-fetching of data into the pixel cache, the graphics pipeline of the present invention is able to take best advantage of the high bandwidth of the memory system while effectively masking the latency of the memory system. More particularly, advantageous reuse of pixel data is enabled by caching, which when combined with pre-fetching masks the memory latency and delivers high throughput. As such, the present invention provides a novel and superior graphics pipeline over the prior art in terms of more efficient data access and much greater throughput. In one embodiment, the present invention is practiced within a computer system having a processor for issuing commands; a memory sub-system for storing information including graphics data; and a graphics sub-system for processing the graphics data according to the commands from the processor.