Abstract: Methods and apparatus for storing data using two-dimensional arrays mapped to memory locations.

Abstract: Methods and apparatus for storing data using two-dimensional arrays mapped to memory locations.

Abstract: A system and method for synchronizing image display and buffer swapping in a multiple processor-multiple display environment. In a master-slave dichotomy, one processor or system is deemed the master and the others act as slaves. The master generates signals used to control vertical retrace and buffer swapping for itself and the slaves. In addition, a synchronization signal generator is provided to synchronize a timing signal between the master and slave systems.

Abstract: A control device, which is capable of suppressing an increase in a load of a data transfer for an increase of an amount of data is provided. The control device includes a compressed data generation unit for generating a compressed data based on a set-up value inputted, and a controller for outputting a frame rate information to the compressed data generation unit, and for making compressed data to be outputted from a memory for use in storing a compressed data to an image display device in accordance with the frame rate.

Abstract: A method of video overlay processing and a system thereof. On-screen display (OSD) data for generating an image on a display device are downloaded to an OSD unit on an integrated circuit. The OSD data are downloaded in bursts separated by gaps. During the gaps, overlay data for generating an overlay on the image are downloaded to an overlay unit on the integrated circuit. The overlay data are divided into portions so that the overlay data can be downloaded in the time between bursts of OSD data. Generally, the amount of overlay data downloaded during a gap is sufficient for generating enough of the overlay until the next gap occurs and the next portion of overlay data is downloaded. Consequently, the size of the memory residing on the integrated circuit for storing overlay data can be reduced to the size needed to store only a portion of the overlay. Furthermore, the bus bandwidth for the OSD is more efficiently utilized.

Abstract: An image display apparatus comprises a line buffer unit which stores binary image data, the binary image data being divided into a plurality of line portion data, each line portion data having a fixed length. Pattern matching units are connected in parallel with the line buffer unit and receives the line portion data respectively, each pattern matching unit determining whether an input pattern of a related line portion data matches with one of reference patterns. When the match occurs each pattern matching unit outputs a truth signal indicating the value one, and otherwise each pattern matching unit outputs a falseness signal indicating the value zero.

Abstract: In one embodiment of the invention, a processor includes an execution pipeline to concurrently execute at least portions of threads, wherein at least one of the threads is dependent on at least another one of the threads. The processor also includes detection circuitry to detect speculation errors in the execution of the threads. In another embodiment, the processor includes thread management logic to control dynamic creation of threads from a program.

Abstract: Methods and apparatus for storing and retrieving data in parallel but in different orders, using three or more memory devices. In one implementation, data for pixels is stored according to a checkered pattern, sequentially among memory devices, forming a checkerboard buffer. In one implementation, a checkerboard buffer includes: a data source, providing data in a first order; a data destination, receiving data in a second order; at least three memory devices each having memory locations, where data is stored in parallel to and retrieved in parallel from the memory devices; a first data switch connected to the data source and each of the memory devices, the first data switch controls which data is stored to which memory device; and a second data switch connected to the data destination and each of the memory devices, the second data switch controls providing data to the data destination according to the second order.

Abstract: Methods and apparatus for implementing a pixel page system providing pixel pages using combined addressing. In alternative implementations, the system stores and retrieves data other than pixel data.

Abstract: A resampling circuit and method where input sample values for samples arranged along a row of a source image are received by a row resampling circuit. The row resampling circuit calculates row output values which are provided to a column resampling circuit that calculates output sample values therefrom. The column resampling circuit includes a shift register that receives the row output values and shifts the row output values through the shift register as the row output samples are calculated. The shift register has a plurality of evenly spaced sample output terminals from which the row output values are sampled by an interpolation circuit for calculation of the output sample values.

Abstract: Methods and apparatus for implementing a pixel page system providing pixel pages optimized for use with a GLV (grating light valve). In one implementation, a system includes: a data source, providing pixel data for pixels in a first order, each pixel in a frame having rows and columns of pixels; a data destination, receiving pixel data for pixels in a second order; at least one memory device including memory pages having memory locations; pixel data for each pixel corresponds to an entry in a pixel page, each pixel page having rows and columns and including pixels, the pixel pages optimized for use with a GLV. Pixel data is stored to memory in the first order and retrieved in the second order. And each memory page stores pixel data in multiple locations according to the first order and stores pixel data in multiple locations according to the second order.

Abstract: Embodiments of the present invention provide a split vertex buffer where the data for each vertex is split between parallel vertex buffers. The first buffer contains vertex X and Y data, while the second parallel buffer contains the remainder of the vertex data. Given the split vertex buffers, the hardware binning-engine is now permitted to read and cache only vertex screen X and Y data. Especially given a typically high level of temporal coherency between indexed vertex references, the reading and caching of large parcels of vertex screen-space X and Y leads to lower and highly efficient utilization of memory bandwidth for hardware binning input. Embodiments of the present invention thus reduce the hardware binning memory bandwidth requirements and improve memory utilization.

Abstract: The coordinate-position inputting/detecting device comprises a lighting device for emitting light into an entry area into which an arbitrary pointing body is inserted to perform an entry operation. At least two image pickup devices are provided with a prespecified space therebetween on a peripheral section of the entry area for picking up images of the pointing body illuminated by the light from the lighting device. Position on the CCD of the image pickup devices where an image of the pointing body is formed is obtained according to output from each of the image pickup devices. Coordinates of the position of the pointing body in the entry area are calculated from these positions.

Abstract: An image processor having a frame memory for storing image data to newly generate purposed image data to be displayed by processing the image data in the frame memory, in which a processing memory for previously storing reference pixel coordinates for processing the image data is included and the data for the reference pixel coordinates in the processing memory is provided for the frame memory as an image-data read address.

Abstract: In a memory consolidated image processing LSI for reading data, a DRAM for storing image data for a plurality of page ranges which are formed by segmenting an image plane corresponding to a display screen in order to page-access a memory region of the DRAM, and image data for a plurality of word ranges which are formed by segmenting each of the page ranges in order to word-access the memory region, is consolidated with an image processing circuit. The size of each of the page ranges is set so that the multiplied value of the power consumption per pre-charge in a power consumption model of a memory by an average number of pre-charges is the substantially minimum value, and the size of each of the word ranges is set so that the multiplied value of the power consumption per word access in the power consumption model of the memory by an average number of word accesses is the substantially minimum value.

Abstract: To increase support a screen having a different aspect ratio or a large screen by use of existing graphics adapters, thus improving performance and flexibility of the whole system. Disclosed is a monitor system comprising a liquid crystal display having a liquid crystal panel which displays an image and has a display area virtually divided into a plurality of divided area, and a plurality of graphics adapters to for developing image data for the divided areas of the liquid crystal display, wherein the divided areas of a screen in the liquid crystal display are obtained by further dividing an area in which the graphics adapters to create images, and a reconstruction circuit for reading out image data developed in the graphics adapters in turn to reconstruct the image data is provided.

Abstract: An image processing apparatus and method, and a display apparatus capable of preventing field tearing caused by memory overrun even when performing a read operation and a write operation of input/output images with respect to a single image memory, wherein a system microcomputer (MC) is used for generating and supplying output delay data for delaying an image output timing based on the write speed to the image memory, the read speed from the image memory, and the read area so that the timing of access to the read end address address and the timing for performing a write operation to the same address match and of a scan converter for receiving the output delay data supplied by the system MC and delaying the image output timing so that the timing of access to the read end address and the timing for performing a write operation to the same address match.

Abstract: A method and system for providing a graphical image on a display of a system is disclosed. The graphical image is provided from data describing a plurality of primitives. The display includes a plurality of pixels. The method and system include providing a plurality of variable-sized bins containing the plurality of primitives and rendering the plurality of primitives by rendering each of the plurality of variable-sized bins variable-sized bin by variable-sized bin.

Abstract: A predictive optimizing unit for use with an interleaved memory and suitable for use in a computer graphics system is described. The unit maintains a queue of pending requests for data from the memory, and prioritizes precharging and activating interleaves with pending requests. Interleaves which are in a ready state may be accessed independently of the precharging and activation of non-ready interleaves.

Abstract: A cache for a graphics system storing both an address tag and an identification number for each block of data stored in the data cache. An address and identification number of a requested block of data is provided to the cache, and is checked against all of the address and identification number entries present. A block of data is provided if both the address and the identification number of the requested data matches an entry in the cache. However, if the address of the requested data is not present, or if the address matches an entry but the associated identification number does not match, a cache miss occurs, and the requested graphics data must be retrieved from a system memory. The address and identification number are updated, and the requested data replaces the former graphics data in the data cache. As a result, a block of data stored in the cache having the same address as the requested data, but having data that is invalid, can be invalidated without invalidating the entire cache.